22 Chip Scale Review March • April • 2020 [ChipScaleReview.com] 3. R. Huemoeller, “Silicon wafer integrated fan-out technology,” Chip Scale Review , Mar/Apr issue 2015. 4. C-F. Tseng, “InFO (wafer-level integrated fan-out) technology,” IEEE 66th Elect. Comp. and Tech. Conf. (ECTC), 31 May – 3 June 2016, Las Vegas, NV, USA, pp. 1-6. 5. W. Li n , “SACQ solde r boa rd- level reliability evaluation and life prediction model for wafer-level packages,” IEEE 67th ECTC, May 30 – June 2, 2017, Lake Buena Vista, FL, USA, pp. 1058-1064. 6. C. K. Yu, “A unique failure mechanism induced by chip to board interaction on fan-out wafer-level package,” IEEE Inter. Rel. Physics. Symp. (IRPS), 2-6 Apr. 2017, Monterey, CA, USA. 7. P. H. Tsao, “Board-level reliability enhancement of WLCSP with large chip size,” IEEE 68th ECTC, May 29 – June 1 2018, San Diego, CA, USA, pp. 1200-1205. 8. W. Fitzgerald, “Advanced low-k die singulation defect inspection and pre- emptive singulation defect detection,” 37th Inter. Elec. Mfg. Tech. Conf., 20-22 Sept. 2016, George Town, Malaysia. 9. Z. Wang, “300mm low-k wafer dicing saw development,” IEEE Trans. Compon. Packag. Technol. Vol. 30, No. 4, Oct. 2007, pp. 313-319. 10. M-K. Shih, “Parameters study of thermomechanical reliability of board- level fan-out package,” Inter. Conf. of Elec. Packaging, 19-22 Apr. 2017, Yamagata, Japan, pp. 66-70. 11. A. Syed, “Updated solder fatigue life prediction models for SnAgCu solder joints,” SMTA, 2006, pp. 939-945. 12. R. Darveaux, “Effect of simulation methodology on solder joint crack growth correlation,” IEEE 50th ECTC, 21-24 May 2000, Las Vegas, NV, USA, pp. 1048-1058. Biographies Gaurav Sharma is a Senior Principal Packaging Engineer at NXP Semiconductors, Austin, TX USA. He has fifteen years of industry experience in advanced semiconductor packaging and holds a PhD in Materials Science and Engineering from Pennsylvania State U. and an MBA from National U. of Singapore. He has published more than forty papers in international journals and conferences. Email firstname.lastname@example.org Nishant Lakhera is Package Development Manager at NXP Semiconductors, Austin, TX USA and holds a PhD in Mechanical Engineering from the U. of Wyoming. He is responsible for development and implementation of electronic packaging solutions for automotive and non-automotive applications. LEADERS IN MICRODISPENSING TECHNOLOGY Our Micro Dispensing product line is proven and trusted by manufacturers in semiconductor, electronics assembly, medical device and electro-mechanical assembly the world over. www.dltechnology.com . 216 River Street, Haverhill, MA 01832 • P: 978.374.6451 • F: 978.372.4889 • email@example.com SMALL REPEATABLE VOLUMES ARE A CHALLENGE, BUT NOT IMPOSSIBLE IF YOU HAVE BEEN CREATING THEM AS LONG AS WE HAVE. TO DO IT WELL, WE PROVIDE THREE THINGS: Dispensing Expertise in a variety of microelectronic packaging applications. Feasibility Testing & Process Verification based on years of product engineering, material flow testing and software control. Product Development for patented valves, dispensing cartridges, needles, and accessories.