Previous Page  10 / 68 Next Page
Information
Show Menu
Previous Page 10 / 68 Next Page
Page Background

Chip Scale Review May June 201

5 [ChipScaleReview.com]

8

Polymer dielectric suppliers have been

working on low-temp cure variations of the

typical PI and PBOs to meet such FOWLP

requirements.

In addition: 1) FOWLP is often

perceived as too expensive; this issue

should be alleviated as the new suppliers

reach HVM; 2) FOWLP imposes a specific

re-design vs. flip-chip solutions are much

more flexible and mature cost-wise; and

3) The window of application for FOWLP

is restricted to die that need an I/O pitch

larger than the chip dimensions can

accommodate, otherwise fan-in or other

solutions will meet the requirements.

It is expected that the mobile industry will

remain the main driver for FOWLP demand

in the future because of its superior RF

performance and its good form factor. The

new FOWLP solutions such as SiP and PoP

will soon allow it to penetrate the industrial,

automotive, and medical markets.

References

1. “Fan-out and embedded die:

technologies and market trends

r e p o r t , ” R e l e a s e d b y Yo l e

Développemen

t (www.yole.fr)

in

Figure 5:

FOWLP challenges and proposed solutions. Courtesy A*Star IME.

Feb. 2015; more information at www. i-micronews.com, reports section.

2. T. Meyer, et al., “Embedded wafer-

level ball grid array (eWLB),”

Electronic Manufacturing Tech.

Symp. (IEMT), 2008, pp. 1-6.

3. “Intel completes acquisition of

Infineon’s wireless solutions

business,” http://newsroom.intel. com/community/intel_newsroom/ blog/2011/01/31/intel-completes- a c q u i s i t i o n - o f - i n f i n e o n - s - wireless-solutions-business.

4. S. Krohnert, et al., “Fan-out WLP —

The enabler for system-in-package

on wafer-level (WLSIP),” Electronic

System-Integration Tech. Conf.

(ESTC), 2012, pp. 1-8.

5. G. Sharma et al., “Performance

and reliability characterization

of eWLB (embedded wafer-level

BGA) packaging,” Electronics

Packaging Tech. Conf. (EPTC),

2010, pp. 211-216.

6. J. Hunt et al., “A hybrid panel

embedding process for fanout,”

El ec t r on i c s Packag i ng Tech .

Conf. (EPTC), 2012 IEEE, pp.

297-303.

7. B. Kesser et al., “The redistributed

chip package: a breakthrough for

advanced packaging,” IEEE Trans.

onAdv. Packaging, Vol. 31, 2008, pp.

39-43.

8. “Freescale and Nepes Corporation

enter into licensing agreement to

manufacture redistributed chip

fan-out package technology,” http://ir.freescale.com/investor- r e l a t i o n s / p r e s s - r e l e a s e -

archive/2010/09122010.aspx.

9. C. C. Liu et al., “High-performance

integrated fan-out wafer-level

packaging (InFO-WLP): technology

and system integration,” IEEE Electron

Devices Meeting (IEDM), 2012, pp.

14.1.1-14.1.4.

10 . H-W. L i u , e t a l . , "Wa r p a g e

characterization of panel fan-out (P-FO)

package," IEEE Elect. Comp. Tech.

Conf., 2014, pp. 1750-1754.

11. H. Hayashi, “A novel wafer-level fan-

out package (WFOP™) applicable

to 50µm pad pitch interconnects,”

Elec. Packaging Tech. Conf. (EPTC),

2011, pp. 730-733.

12. “TSMC acquires Qualcomm’s

facility in Longtan, Taoyuan,” http://

technews.co/2014/11/21/tsmc- acquires-qualcomms-facility-in- longtan-taoyuan/.

13. A. Katsumata, “New embedded

package technology using large-

scale panel (FO-WLP),” IEEE

Santa Clara Valley Chap., IEEE

CPMT, Feb. 21, 2013.

14. Yole Développement, “Fan-out

and embedded die: technology

and market trends report,” http:// www.i-micronews.com/advanced- packaging-report/product/fan-out- and-embedded-die-technologies- market-trends.html.

Biographies

Jérôme Azémar received his Master’s

in Microelectronics and Applied Physics

from INSA Toulouse and is a Technology

& Market Analyst, Advanced Packaging

& Manufacturing at Yole Développement;

email:

azemar@yole.fr

Phil Garrou received his PhD in

Chemistry from Indiana U. He has served as

President of IEEE CPMT (2004-2005) and

IMAPS (1998) and is currently a Sr. Analyst

for Yole Développement.