Previous Page  5 / 68 Next Page
Information
Show Menu
Previous Page 5 / 68 Next Page
Page Background

Chip Scale Review May June 2015

[ChipScaleReview.com]

3

CONTENTS

Volume 19, Number 3

The International Magazine for Device and Wafer-level Test,

Assembly, and Packaging Addressing

High-density Interconnection of Microelectronic IC's

including 3D packages, MEMS, MOEMS,

RF/Wireless, Optoelectronic and Other

Wafer-fabricated Devices for the 21st Century.

STAFF

Kim Newman Publisher knewman@chipscalereview.com Lawrence Michaels Managing Director/Editor lxm@chipscalereview.com Debra Vogler Senior Technical Editor dvogler@chipscalereview.com

CONTRIBUTING EDITORS

Dr. Thomas Di Stefano Contributing Editor - Test tom@centipedesystems.com Roger H. Grace Contributing Editor - MEMS rgrace@rgrace.com Jason Mirabito Contributing Editor - Legal jason@isusip.com Dr. Ephraim Suhir Contributing - Editor - Reliability suhire@aol.com

EDITORIAL ADVISORS

Dr. Andy Mackie (Chair)

Indium Corporation

Dr. Rolf Aschenbrenner

Fraunhofer Institute

Dr. Thomas Di Stefano

Centipede Systems

Joseph Fjelstad

Verdant Electronics

Dr. Arun Gowda

GE Global Research

Dr. John Lau

ASM Pacific Technology

Dr. Venky Sundaram

Georgia Institute of Technology-

3D Systems Packaging Research Center

Dr. Leon Lin Tingyu

National Center for Advanced

Packaging (NCAP China)

Francoise von Trapp

3D InCites

SUBSCRIPTION--INQUIRIES

Chip Scale Review

All subscription changes, additions, deletions to any and

all subscriptions should be made by email only to

subs@chipscalereview.com

Advertising Production Inquiries:

Kim Newman knewman@chipscalereview.com

Copyright © 2015 Haley Publishing Inc.

Chip Scale Review (ISSN 1526-1344) is a registered trademark of

Haley Publishing Inc.All rights reserved.

Subscriptions in the U.S. are available without charge to qualified

individuals in the electronics industry. Subscriptions outside of the

U.S. (6 issues) by airmail are $100 per year to Canada or $125 per

year to other countries. In the U.S. subscriptions by first class mail

are $95 per year.

Chip Scale Review, (ISSN 1526-1344), is published six times a

year with issues in January-February, March-April, May-June, July-

August, September-October and November-December. Periodical

postage paid at Los Angeles, Calif., and additional offices.

POSTMASTER: Send address changes to Chip Scale Review

magazine, P.O. Box 9522, San Jose, CA 95157-0522

Printed in the United States

FEATURE ARTICLES

SÜSS MicroTec Inc. | Phone: +1 408 940 030 0 | www.SUSS.com + ProjecTIon LIThograPhy Innovative exposure Solutions for 3D Packaging, Wafer-Level Packa- ging and Flip chip applications Read article on page 48 Dispensing technologies in semiconductor packaging Akira Morita, Garrett Wong, Dan Ashley Nordson ASYMTEK 14 Semiconductors and packaging for the Internet of Things John H. Lau ASM Pacific Technology Ltd. 25 In-line process monitoring of advanced packaging processes using focused beam ellipsometry Jay Chen, Jian Ding Rudolph Technologies, Inc. and Parker Huang SPIL 34 Advanced wafer-level technology: enabling innovations in mobile, IoT and wearable electronics Seung Wook Yoon, Boris Petrov, Kai Liu STATS ChipPAC 54 Next-generation 3D FPGAs Xin Wu, Woon-Seong Kwon, Suresh Ramalingam Xilinx 20 GaN-on-Si CSP LEDs Zainul Fiteri Plessey Semiconductors 31 3D thermal simulation in the IC design flow John Parry Mentor Graphics Corporation 39 Projection lithography performance using full-field exposure technology Ralph Zoberbier SÜSS MicroTec Lithography GmbH 48 Critical challenges in advanced 3D integration: a metallization overview Thierry Mourier CEA-Leti 43