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Chip Scale Review May June 2015

[ChipScaleReview.com]

5

Fan-out packaging: what can explain such

a great potential?

By Jérôme Azémar, Phil Garrou

[Yole Développement]

afer-level packaging (WLP)

has proven to be a high-

performance, low-cost

option for many applications

such as consumer mobile products. We

believe that at a given pitch, WLP is limited

in the I/O it can provide since all the I/O pads

have to fit within the area of the die. Fan-

out packaging was developed to supply an

increased number of I/O for such cases. Fan-

out packaging is usable for single-chip, multi-

chip, and system-in-package (SiP) assembly

and can easily be extended to support

package-on-package (PoP) configurations.

Furthermore, we expect a $200M fan-out

WLPmarket in 2015 with 30%CAGR in the

coming years. What can explain such a great

potential [1]?

Fan-out WLPs (FOWLP) are typically

“re-configured” by placing known good

ICs active face down on a foil and over-

molding them. The foil is then removed

and the resultant plastic wafers are flipped

and processed in a wafer fab. Front-end

isolation and metallization redistribution

layer (RDL) processing is then used to fan

out the interconnections to the surrounding

area with lithography and patterning wafer-

level processes. Next, solder balls are

applied and testing is performed on-wafer.

The reconstituted wafer is then sawn into

individual units, which are packed and

shipped. As a WLP, fan-out wafer-level

packaging (FOWLP) eliminates the printed

circuit board (PCB) substrate as well as the

need to use wire bonding or flip-chip bumps

to establish electrical contacts. Without a

PCB, the package is inherently thinner,

which is a feature in great demand for today’s

mobile products (

Figure 1

).

With the fan-in WLP approach, the

number of interconnects and their pitch

must be adapted to the chip's size. FOWLP,

by contrast, supports a fan-out area that is

adaptable and which has no restriction on ball

pitch. The FOWLP approach, not constrained

by die size, can provide design flexibility

to accommodate an unlimited number of

interconnects between the package and the

board for maximum connection density,

finer line/spacing, improved electrical and

thermal performance, and small package

dimensions to meet the relentless form factor

requirements and performance demands of

the mobile market.

Development of fan-out wafer-level

packaging

The Infineon e-WLB (embeddedwafer-level

BGA) technology [2] was commercialized

in volume, in early 2009. Infineon’s chip

was a wireless baseband SoC with multiple

integrated functions (GPS, FM radio, BT,

etc.). LGE, Samsung (baseband modem), and

Nokia (baseband modem and RF transceiver)

have used Infineon’s eWLB in their cell

phone products. The Infineon eWLB wireless

business was acquired by Intel in 2011 [3].

The Infineon technology was subsequently

licensed to OSATS NANIUM [4], STATS

ChipPAC [5] and ASE [6] which created

a supply chain infrastructure with multi-

sourcing capability. While STATS ChipPAC

and NANIUM have been steady, consistent

suppliers since their licensing and subsequent

scale-up, ASE dropped production a few years

ago and recently has resumed production with

the Infineon-based technology as well as in-

house developed fan-out technologies.

Freescale’s redistributed chip package (RCP)

process [7], is a similar technology that has

been licensed to Nepes, who to date has very

limited productionwith that technology [8].

FOWLP technologies are also being

developed by TSMC [9], SPIL [10], J-Devices

[11] and others. None are currently in HVM

and will initially lack the multi-sourcing

available with eWLB. TSMC recently

purchased a plant in Taiwan from Qualcomm

and reportedly is turning it into a facility

devoted to the development of their advanced

integrated fan-out wafer-level packaging

(InFO-WLP) technology. TSMC reports

manufacturing will commence in 2016

depending on “customer demand” [12].

SPIL has discussed its efforts to

commercialize a panel fan-out package concept

W

Figure 1:

Process flow for standard Infineon eWLB fan-out packaging. SOURCE: Fan-Out and Embedded Die:

Technologies & Market Trends Report – Feb. 2015

MARKET UPDATE