Chip Scale Review May June 2015 [ChipScaleReview.com]
by combining PCB, semiconductor back-
end, semiconductor WLP and LCD Gen 2.5
glass (370X470mm) processing technologies
. This effort requires high-accuracy die
bonding and die shift compensation at
film lamination, lower warpage sheet form
film lamination, good copper trace plating
uniformity control at large panel area, and also
precise photolithographic technique. Known
good die are reconstructed on the LCDGen 2.5
glass carrier with adhesive temporary bonding
material. Processing issues are identified as
warpage, die shift “coordinates compensation
at lithography” and Cu plating uniformity.
J-Devices is also attempting to develop
panel based processing for low-cost
fan-out packaging technology [11,13]. The
J-Devices wafer fan-out package (WFOP) is
compared to the eWLB in the following table
). The metal plate serves to minimize
warpage and decrease thermal issues. Greater
than 1000hrs of package and board-level
reliability have been achieved. It should be
stated that such J-Devices’ panel production is
not yet in high-volumemanufacturing (HVM).
The second-generation of FOWLParemulti-
chip structures including familiar PoP and SiP
architectures and the incorporation of passives.
Double-sided and stacked solutions are created
by through-mold vias (TMV). These new
multi-die solutions are also available from
STATS ChipPAC, ASE and NANIUM. Such
packages are generating increased interest in
this packaging technology (
The FOWLP market
Yole’s analysts estimate that the 2014
market for FOWLP is ~$174MM with
STATS ChipPAC having the largest share
at 59% of the market (
several new suppliers coming on line, we
see the market growing at a 30% CAGR to
>$600MM by 2020.
Despite its many positive attributes,
challenges remain for FOWLP that impede its
widespread adoption. IME has initiated aHigh-
Density FOWLP Consortium that includes
Amkor, NANIUM, STATS ChipPAC, NXP,
GLOBALFOUNDRIES, K&S, Applied
Materials, TOK, KLA-Tencor, SPTS, and
others . Their compilation of challenges
and proposed solutions is shown in
The two main challenges of fan-out
packaging are die shift and warpage of the
molded wafer. Die shift impacts the alignment
of the RDL on the die pad. Changes in die
positions are caused by thermal expansion of
the carrier during molding and shrinking of
the mold compound upon cooling. Warpage
impacts equipment handling. Processing
equipment will not accept the molded wafer
if warpage is too high. Proper selection of
the mold compound and optimizing molding
process conditions are therefore needed to
minimize warpage of the molded wafer.
Finding the proper RDL insulator with a
low-temperature cure has been a lingering
problem. Typical materials with cure
temperatures > 250C cannot be used because
they exceed the T
of the molding resins.
PComparison of J-Devices’ WFOP™ to the Infineon eWLB.
SOURCE: Yole Développement.
Second-generation FOWLP packaging options. SOURCE: Fan-Out and Embedded Die:
Technologies & Market Trends Report – Feb. 2015.
S2014 FOWLP revenue ($MM). SOURCE: Fan-Out and Embedded Die: Technologies & Market Trends
Report – Feb. 2015.