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Chip Scale Review May • June • 201

6 []

FO-WLP has been an available

solution for over five years, and

is now getting increased attention.

Le a d i ng OSATs s u c h a s STATS

ChipPAC (a JCET company), ASE,

SPIL, Amkor, and NANIUM S.A.

h a v e s e e n a s i g n i f i c a n t u p t i c k

in interest for products over the

past 12 months. No fewer than 12

fabless and IDM companies are in

the process of qualifying dozens of

design wins using this approach.

Most of the FO-WLPs to date focus

o n sma l l e r d i e / p a c k a g e s u p t o

8x8mm. Over the course of 2016,

we expect to see 1-2 die packages

wi t h up t o 500 I /O f o r mu l t i p l e

applications and companies. Most

produc t i on of FO-WLP so f a r i s

focused on 1-2 layer RDLs at 10-

15µm L/S.

As the shift from lead frame to

substrate to wafer-based packaging

evolves, Prismark expects the supply

Impact of wafer-based packaging on the

supply chain

By Brandon Prior

[Prismark Partners LLC]

he past twenty years have

s e e n a n e no rmou s s h i f t

in packaging approaches

used for integrated circuits

(ICs). In that time, we have moved

from over 95% of die going in to lead

frame packages to about 60% of units

today. From a revenue perspective,

85% of all package assembly is into

package types that did not exist 20

years ago.

The shift to customizable substrate-

based array packages was one of

ma n y k e y f a c t o r s c o n t r i b u t i n g

t o t he g r owt h o f t he ou t sou r ced

semiconductor assembly and test

(OSAT) market. Though many OSATs

started with quad flat package (QFP)

and other lead frame packaging,

today, a significant portion of their

r e v e n u e s c ome f r om s u b s t r a t e -

based array packages. Substrate-

based packages first emerged twenty

years ago as an alternative to lead

frame packages, and since that time

have grown to represent 16% of IC

package units, but closer to 68% of all

IC package value. We will continue

to see improvements and evolution in

substrate-based packages, and they

will remain the packages of choice for

most all advanced requirements. More

recently, the growth of packaging

solutions completed in wafer format,

i nc l ud i ng WLCSP, FO-WLP and

2 . 5 / 3D TSV, ha s p r omp t ed bo t h

OSATs and wafer foundries to address

this growing opportunity.

A l t h o u g h m a n y c a p t i v e

s e m i c o n d u c t o r o p e r a t i o n s a r e

building WLCSP internally, OSATs

and increasingly, foundries, continue

to represent the fastest growth of

capacity to serve both fabless and

IDM customers. We are also seeing

WLCSP commonly adopted in other

segments beyond smartphones and

t ab l e t s . The s e s egmen t s

include wearables/Internet

o f Th i ngs ( oT) /med i ca l ,

u l t r a - m o b i l e P C a n d

automotive applications.

T h o u g h s ome c o n c e r n s

remain in terms of cost,

r e l i a b i l i t y a n d e a s e o f

a s s e m b l y , i m p r o v e d

versions of WLCSP have

a l l o w e d a d o p t i o n f o r

i n c r e a s i n g c omp l e x i t y

devices (

Figure 1


This adoption of WLCSP

in new segments will be

e n a b l e d b y t h e s e c o n d -

g e n e r a t i o n o f WL C S P

p a c k a g e a p p r o a c h e s ,

including, but not limited to:

• Protected or enhanced

WLCSP: These off e r

p r o t e c t i o n o n f i v e s i d e s o f

the die, which should enable

improved package reliability and

easier handling for surface mount

technology (SMT) assembly. This

technology is being explored for

small die sizes.

• WLC S P w i t h o u t RDL : D i e

des i gned for f l i p- ch i p a t t ach

without RDL keep the cost of

WLCSP low. Many companies

have been using this “bump on

pad” approach for years.

• Fan-out wafer-level package (FO-

WLP): These offer significantly

added flexibility with multi-chip,

package-on-package (PoP), and

broader final pitch configurations

t h a t c a n b e b u i l t . Wh i l e n o

longer a die size package, the

RDL processing is still wafer-

based, and already offers thinner

p a c k a g e s a n d f i n e r r o u t i n g

capabilities than substrate-based

solutions of today.



Figure 1:

A Dialog PMIC. a) (top) The Dialog PMIC device found

in the iPhone 6S measures 7.2 x 7.5mm, with a thickness of less

than 0.4mm. b) (bottom) It has 380 I/Os, and utilizes a fan-in WLCSP

structure with 1 metal layer RDL at 15µm line/space. The large

die size requires underfill on this main board assembly. SOURCE:

Prismark Partners LLC / Binghamton University