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Chip Scale Review May • June • 2016


chain to change as well.

Table 1

highlights the significance of OSATs

in the substrate/array-based packages,

and the importance of both the OSATs

and the wafer foundries in forecasting

wafer-based packaging.

Wafer foundries entering advanced


The major story in the FO-WLP

segment is the ongoing investment by

TSMC with its integrated fan-out (InFO)

package. It is now widely presumed

that the Apple A10 processor will be

the first large die adoption of FO-WLP

technology. This may be a notable

turning point for wafer foundries to

enter the packaging domain. While

speculations mount on whether second

location/source will be required, TSMC

appears committed to growing its back-

end business.

From a business perspective, the

entrance of wafer foundries and “mid-

end” service providers may change the

landscape for packaging. TSMC has

aggressive growth targeted for back-end

processing. The company is currently

investing more in FO-WLP than all other

OSATs combined. Meanwhile, other

foundries are considering joint ventures

and developments in this sector.

The offering of post-fab processing

of semiconductors is logical for wafer

foundries, especially while still in

wafer format. For years, TSMC and


offering wafer bumping services.

Standard fan-in WLCSP has also

been offered by TSMC, but was not

necessarily a major focus. In addition,

pure play foundries see legitimate threat

from vertically integrated players such

as Samsung and Intel that offer turn-key

foundry and package solutions. At the

heart of the TSMC InFO development

justification would be the success at

capturing 100% of the Apple A10

foundry business.

Ot he r wa f e r foundr i es such as

SMIC and UMC are involved in wafer

bumping partnerships as well, getting

some wins in the Si Interposer domain.

Meanwhile, TSMC has continued

to increase its presence in back-end

processing including: 1) Wafer bump

and test business; 2) Chip-on-wafer-

on-substrate (CoWoS) technology for

2.5D interposers; 3) Integrated fan-

out wafer-level package (InFO-WLP);

and 4) Expansion of WLCSP and

wafer bumping.

Similar to the early days of flip-

chip with stand-alone wafer bumpers,

WLCSP, fan-out WLCSP, 2.5D and

3D has spurred a few companies to

emerge. Most of these companies offer

(or are preparing to offer) wafer-based

package assembly services: DECA

Technologies, ALLVIA, TEZZARON/

Novati, ANCSi, Tessera/Ziptronix. There

are also a couple emerging WLCSP

players in China that focus on image

sensor and other specialty wafer-based

package solutions.

Going forward, we expect wafer

foundries and other wafer-based package

solution providers to continue to target

the mid-end segment. Some customers

may see value in a turnkey/integrated

offering from a wafer foundry, but more

critically, the emerging of WLCSP and

2.5/3D segments in high volume will

eventually lead to additional mid-end

offerings by foundries. However, OSATs

have a significant head start, and by 2020,

will likely capture 45-50% of the wafer-

based packaging business, compared

to about 35% today. The heavily cited

AMD Graphics card comprising 3D

TSV and silicon interposer, utilized

wafer and back-end packaging solutions

at captive, OSAT, and wafer foundry

locations (

Figure 2


Investment and consolidation

TSMC’s 2016 capital spending plan

of $9-10Bn is ten times that of even the

largest OSATs. The company expects

that about 10% will be for the back-end,

most of which is for the InFO package.

This scale of investment for wafer-based

packaging at TSMC is unprecedented.

In the past, perhaps only Intel would

have had such large investments within

packaging. To keep up with these

investment levels, we may see more

consolidation of OSATs to compete in this

domain. There has already been a major

wave of consolidation with both fabless

and IDM semiconductor companies.

Typically, as industries mature,

participants consolidate to gain market

share advantages. Within the electronics

industry supply chain, there has been an

Table 1:

Package assembly value by segment.

SOURCE: Prismark Partners LLC

Figure 2:

An AMD Fury X graphics processor comprising the following: a) (left) A 28x 35mm Si interposer from

UMC that connects the GPU die to high-bandwidth memory stacks; and b) (right) The interposer has 3RDLs at

2.5µm line/space with 10µm diameter TSVs. SOURCE: Prismark Partners LLC / Binghamton University