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Chip Scale Review May • June • 2016


Comparison between wet and dry silicon via reveal in

3D backside processing

By Dave Thomas, Janet Hopkins, Huma Ashraf, Jash Patel, Oliver Ansell

[SPTS Technologies]

and Anne Jourdain, Joeri De

Vos, Andy Miller, Eric Beyne


Originally distributed at the International Wafer-Level Packaging Conference, San Jose, CA Oct. 13-15, 2015

afer backside processing

is critical for 3D-IC wafer

stacking. Through-silicon

vias (TSVs) typically formed using via-

middle processing, are usually exposed

from the backside of 300mm device

wafers by the combination of mechanical

grinding and wet or dry etch processes.

A fast via reveal etch is required to

have a productive etch rate, but also to

have the precision necessary to control

within wafer uniformity, selectivity to

thin TSV liners and smoothness of post-

etch surfaces. This makes in situ end

point detection essential for controlled

processing, especially as the target tip

height is reduced to minimize cost.

This paper compares imec’s current

wet chemical process of record with

SPTS’s dry etch approach. With the

dry technique, 1µm nail heights can

be controlled within 300nm in order to

minimize the overall cost per wafer by

eliminating the need for rework steps.

The applicability of such a process to

extreme wafer thinning to 5µm final Si

thickness is also demonstrated.

3D technologies hold the promise

to further enable system performance

increase in a time where device scaling

has become increasingly challenging.

Among the many 3D options that are

being explored and developed today, the

3D-stacked IC (or 3D-SIC) approach

has become a mature and economically

viable technology and provides the

highest density for 3D interconnects to

date [1]. 3D stacking and interconnecting

components through TSVs is intrinsically

limited to the stacking of thin dies or

wafers, typically ranging from 100µm

down to 10µm or lower. The most

commonly used approach nowadays is

via-middle where the TSVs are made

after completion of the front-end-of-

line (FEOL) and before the back-end-

of-line (BEOL). The formation of TSVs

is not the only crucial element of 3D

chip stacking. Backside processing,

including wafer thinning and TSV reveal,

is essential to access the TSVs from

the wafer backside in order to make the

required electrical connections during

the 3D assembly process. Thinning of the

device wafer uses a carrier wafer system

to provide mechanical support. Achieving

precise thickness control of the thinned

wafer on carrier is critical for successful

subsequent TSV reveal, passivation layer

deposition, metal redistribution and

bumping. In this via-middle approach,

the starting residual silicon thickness

above the via tips (also called TSV

nails) can vary within a few microns,

because of incoming accumulating

n o n u n i f o r m i t i e s f r o m t h e T S V

frontside etching, wafer bonding and

wafer thinning processes, as shown in

Figure 1

. This makes in situ end point

de t e c t i on e s s en t i a l f o r con t r o l l ed

processing, especially as the target

nail height is reduced to minimize

the cost.

Options for TSV reveal processing

In the via-middle integration scheme,

the main purpose of backside processing

is to expose the buried TSVs in order to

make the future inter-die connections.

Two approaches can be used for the via

reveal processing.

One approach (“flat reveal”) consists

of grinding the Si bulk until the TSVs are

reached. In this case Cu within the TSVs

comes into contact and contaminates the

Si wafer backside. This may be a risk

for Si die <50µm thick. The approach

is useful when depth variations of the

Cu TSVs are large (multiple microns of

within-wafer variation) and/or the thin

wafer thickness variation (TTV) is large


The second approach (“soft reveal”)

i s p r e f e r r e d b e c a u s e i t p r e v e n t s

backside Cu contamination issues. Here

the mechanical grinding is stopped

before the first Cu TSVs are reached.

Some silicon remains between the

wafer backside and the tip of the TSVs,

the so-called residual silicon thickness

(RST). When the frontside TSV depth

is controlled within tight tolerances

(below 1µm within-wafer variation)

and the wafer thinning on carrier results

in a low TTV, the resulting variation

of the RST can be very small, in the

range of a few µm. The remaining

Si etch to expose the TSVs has to be


Figure 1:

Illustration of a TSV device wafer on carrier after thinning. The residual Si thickness above the TSVs is the

sum of all process contributors (TSV depth variation, bonding and thinning process variation).