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Chip Scale Review May • June • 2016


done s e l e c t i ve l y t o

the oxide liner. The

TSV i s p a s s i v a t e d

wi t h d i e l e c t r i c and

subsequently etched

or CMP’d to expose

the Cu [2]. Soft reveal

e t c h i n g c a n e i t h e r

be done using a wet

or a dry process. An

illustration of the soft

via reveal process is

shown in

Figure 2


This paper compares

ime c ’s c u r r e n t we t

chemical via reveal

p r o c e s s o f r e c o r d ,

based on the selective TMAH chemistry,

with SPTS’s dry etch via reveal, based

on an SF


plasma. State-of-the-art

metrology has been used to image large

arrays of revealed TSVs. Data on nail

height control and uniformity, liner

selectivity and surface roughness are

presented and discussed.


The imec process of reference (POR)

is wet and uses TMAH solution with

a center dispense as shown in



. Although this process has a good

uniformity (<±3% variation across a

300mm wafer) and a high selectivity

to oxide (>1000:1), the etch rate is low

(about 1µm/min), and the current set-

up does not offer end point detection.

This makes the process difficult to

control as multiple reworks are very

often required to achieve the target

TSV nail height.

Imec has also investigated a second

option of a fast dry Si etch that offers

a similar uniformity (<±3%) and a

high selectivity to oxide (180:1). This

process, based on an SF


plasma, can

deliver an etch rate >9µm/min and is

offered together with an in situ end

point detection system capable of

detecting the presence of the Cu TSVs.

This means that the reveal etching

is fast and controlled and no longer

requires any rework.

A 3 0 0mm SPTS Ra p i e r s y s t em

was used for the dry via reveal. The

p r oce s s comb i ne s h i gh RF sou r ce

power (~4kW) with a high gas flow

to maximize etch rate. Uniformity

is controlled by separating the RF

powers and gas inlets into primary

and secondary locations—referred

t o a s d u a l - s o u r c e d e s i g n [ 3 ] . A

uniform, highly dissociated plasma

( w i t h a h i g h n e u t r a l F r e a c t a n t

density) is thereby exposed to the

wafer. The temperature of the wafer

is controlled using an electrostatic

chuck. RF bias power is minimized in

order to maximize selectivity to the

liner oxide. This makes the etching

mechanism highly chemical in nature

with the final etch product being SiF



Figure 4

is a schematic of the Rapier

plasma chamber.

More recent wafers have been run

on an SPTS Rapier XE module. This

includes productivity enhancements

to the Rapier design that increases the

source power to ~8kW and increases

the available gas flows. The result is

a significant increase in etch rate (by

a factor of ~2). Both plasma chambers

include an in situ end point detection

system known as ReVia



Prior to reveal etching, the wafers are

thinned down on carriers by standard

r ough a nd f i n e g r i nd i ng [ 2 ] . Th e

Figure 3:

Photo of a 300mm wafer after TSV wet

reveal a) and microscope picture of revealed TSVs b).

Figure 4:

Rapier process module used for dry via

reveal etching in an SF



Figure 5:

Top Si thickness variation across a 300mm wafer after thinning to a target value of 56µm.

Figure 2:

Illustration of the soft via reveal process.