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Chip Scale Review May • June • 2016

[ChipScaleReview.com]

CONTENTS

Volume 20, Number 3

The International Magazine for Device and Wafer-level Test,

Assembly, and Packaging Addressing

High-density Interconnection of Microelectronic IC's

including 3D packages, MEMS, MOEMS,

RF/Wireless, Optoelectronic and Other

Wafer-fabricated Devices for the 21st Century.

STAFF

Kim Newman Publisher knewman@chipscalereview.com Lawrence Michaels Managing Director/Editor lxm@chipscalereview.com Debra Vogler Senior Technical Editor dvogler@chipscalereview.com

CONTRIBUTING EDITORS

Roger H. Grace Contributing Editor - MEMS rgrace@rgrace.com Jason Mirabito Contributing Editor - Legal jason@isusip.com Dr. Ephraim Suhir Contributing - Editor - Reliability suhire@aol.com

EDITORIAL ADVISORS

Dr. Andy Mackie (Chair)

Indium Corporation

Dr. Rolf Aschenbrenner

Fraunhofer Institute

Joseph Fjelstad

Verdant Electronics

Dr. Arun Gowda

GE Global Research

Dr. John Lau

ASM Pacific Technology

Dr. Leon Lin Tingyu

National Center for Advanced

Packaging (NCAP China)

SUBSCRIPTION--INQUIRIES

Chip Scale Review

All subscription changes, additions, deletions to any

and all subscriptions should be made by email only to

subs@chipscalereview.com

Advertising Production Inquiries:

Kim Newman knewman@chipscalereview.com

Copyright © 2016 Haley Publishing Inc.

Chip Scale Review (ISSN 1526-1344) is a registered trademark of

Haley Publishing Inc.All rights reserved.

Subscriptions in the U.S. are available without charge to qualified

individuals in the electronics industry. In the U.S. subscriptions by first

class mail are $125 per year. Subscriptions outside of the United States

are $225 per year to other countries.

Chip Scale Review, (ISSN 1526-1344), is published six times a

year with issues in January-February, March-April, May-June, July-

August, September-October and November-December. Periodical

postage paid at Los Angeles, Calif., and additional offices.

POSTMASTER: Send address changes to Chip Scale Review

magazine, P.O. Box 9522, San Jose, CA 95157-0522

Printed in the United States

FEATURE ARTICLES

Your yield. Your profitability. Your reputation depends on 100% quality assurance for every wafer, device and package. Sonix is the leader in ultrasonic technology and expertise for inspecting wafer bonds, device interconnects and package integrity. Find smaller defects faster, at any layer. Learn more and request a free sample analysis at Sonix.com . QUALITY IS EVERYTHING © 2016 Sonix, In. All rights reserved. Advanced testing technology for emerging automotive applications Dan Stillman Texas Instruments Amy Leong, Ashish Bhardwaj FormFactor, Inc. 18 What is driving advanced packaging platforms development? Thibault Buisson, Santosh Kumar Yole Développement Ron Huemoeller Amkor Technology 32 Design, material, process, and equipment of embedded fan-out wafer/panel-level packaging John H. Lau, Nelson Fan, Li Ming ASMPacific Technology Ltd. Comparison between wet and dry silicon via reveal in 3D backside processing Dave Thomas, Janet Hopkins, HumaAshraf, Jash Patel, OliverAnsell SPTS Technologies Anne Jourdain, Joeri De Vos,AndyMiller, Eric Beyne imec 38 Current state and evolving trends in MEMS packaging MehranMehregany CaseWestern Reserve University 51 Automated inspection between the die improves yield and reliability Scott Balak Rudolph Technologies, Inc. 57 Final test solution for WLCSP devices Andy Nagy Xcerra 59 Plasma dicing methods for thin wafers Christopher Johnston Plasma-Therm LLC 54 45 Chips “face-up” panelization approach for fan-out packaging Boyd Rogers, Debbie Sanchez, Craig Bishop, Cliff Sandstrom, Chris Scanlan, TimOlson Deca Technologies, Inc. 24