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Chip Scale Review May • June • 2016

[ChipScaleReview.com]

Major OSATs positioned for growth opportunities in SiP

By TechSearch International and Chip Scale Review staff

n a series of interviews,

Chip

Scale Review

and TechSearch

International asked several

major outsourced semiconductor

assembly and test companies (OSATs)

to comment on their view of system-

in-package (SiP) technology and how

they are positioned to meet the growing

demand. In today’s world of mobile

product introductions that must ramp in

four to five months and may only have a

lifetime of a year, SiP is essential to the

success of new products in this space.

The physical form of a SiP is a module

that often includes mechanical features

such as shielding, heat sinks, antennas,

and/or connectors. There are many

different configurations of SiP modules

(2D/2.5D/3D) that are customized for

specific end applications to leverage

a variety of potential benefits offered

by SiP, including performance, cost,

form factor, and time-to-market. SiP

solutions may require multiple packaging

technologies such as fine-pitch flip-chip,

wire bonding, wafer-level packaging

(WLP) and fan-out WLP (FOWLP),

integrated passive devices, and embedded

die, as well as advanced substrates,

high-density surface mount technology

(SMT), enhanced molding processes,

shielding, and system-level design

and test. In addition to multi-die flip-chip

packages, hybrid package designs with

stacked wire bonding die on FC die, or

in side-by-side configurations, integrated

with a number of passives, are examples

of 2D SiP package technologies in use

today. A recent report from TechSearch

International shows a compound annual

growth rate of slightly more than 13% in

the areas of mobile, wearable, consumer,

and select computing, communication,

a n d a u t o m o t i v e e l e c t r o n i c s

(

Figure 1

). Several major OSATs are

targeting this market with varying

capabilities. Below is a summary of the

responses to interview questions posed to

several OSATs.

Q: How do you define SiP?

Amkor

: Amkor defines advanced SiPs

as multi-component, multi-function in an

IC package. SiP integrates more than one

semiconductor component of different

functionalities into a single package form.

ASE

: ASE defines an SiP module

as a package or module that contains

a functional electronic system or sub-

system that is integrated and miniaturized

through IC assembly technologies. It is

important to note that the module is a

“system or subsystem.” There are many

multi-die packages with surface mount

technology (SMT) components being

manufactured, but they may not perform

system-level functionality. If a system-

level test were performed on the module,

then it would fit into this SiP definition.

It is also important to highlight the

achievement of miniaturization using IC

assembly technologies. There are many

small modules fabricated using traditional

SMT methods. If an IC process such as

die attach, wire bonding, transfer molding

or any other process common to IC

assembly is used, then it would fall into

this definition.

STATS ChipPAC

: SiP is a functional

electronic system or sub-system that

includes two or more heterogeneous

semiconductor die (often from different

technology nodes optimized for their

individual functionalities), usually with

passive components.

SPIL

: SiP is a hybrid solution for

system integration.

UTAC

: SiP is a heterogeneous

integration into a standard package format

such as ball grid array (BGA), land grid

array (LGA), and lead-less or leaded lead

frame. SiPs typically contain multiple ICs

with diverse device functions such as logic

and memory, RF or analog plus digital

I

MARKET UPDATE

Figure 1:

2015 SiP market by device type (shares of packages shipped). SOURCE: TechSearch International