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12

Chip Scale Review May • June • 2018

[ChipScaleReview.com]

better and simpler process is shown in

Figure 2

[5]. It can be seen that for the

PI (polyimide) development, the whole

reconst it ut ed wafe r is spi n- coat ed

with a photosensitive PI. It is followed

by applying a stepper and then using

photolithography techniques to align,

expose, and develop the vias of the PI.

Finally, the PI is cured at 200°C for

one hour—this will form a 5µm-thick

PI layer. It is followed by sputtering

Ti and Cu by PVD at 175°C over the

entire reconstituted wafer. Then, apply

a photoresist and a stepper and use

photolithography techniques to open

the redist r ibution t race’s locations.

Nex t , elect roplat e t he Cu by ECD

at room t empe r at u re on t he Ti /Cu

i n t he photoresist open i ngs. These

steps are followed by stripping off the

photoresist and etching off the Ti/Cu;

RDL1 is thereby obt ained. Finally,

repeat all the above steps to obtain

other RDLs.

Figure 3

shows the cross

sect ion of a FOWLP with 2 RDLs.

Th is can be used for FOWLP wit h

chip-f irst and chip-last processing.

The RDLs made by the polymer (either

photosensitive or not) and ECD Cu +

etching are called organic RDLs.

FOWLP RDLs by PECVD and

Cu - Dama s c e n e + CMP.

T h i s i s

t he oldest back- end semiconductor

process. Th is process uses SiO

2

or

SiN for the dielectric layer and ECD

to deposit the Cu on the whole wafer.

That is followed by usi ng CMP to

remove the overburden Cu and seed

layer to make the Cu conductor layer

of the RDLs. The key process steps

a r e shown i n

F i gure 4

. Fi r s t , u s e

PECVD to form a thin layer of SiO

2

(o r Si N ) on a f u l l t h ick ne s s ba r e

si l icon wa fe r a nd t hen u s e a s pi n

coater to lami nate t he photoresist.

These steps a re followed by usi ng

a st eppe r t o open t he r e sist a nd a

react ive ion et ch (R I E) t o remove

t he SiO

2

. The n , a s t e pp e r i s u s e d

to open the resist wider and RIE to

et ch more of t he SiO

2

. Next , st r ip

off the resist, sputter the TiCu, and

ECD t h e Cu on t h e whol e wa f e r.

The se st eps a r e fol lowed by CMP

t o r emove t he ove r bu r den Cu a nd

the TiCu, and then we have the first

RDL1 and V01 (the via connecting

t h e S i a n d R DL1) a s s h ow n i n

Figure 5

[2]. This is called the dual

Cu- damascene method [2]. Finally,

repeat all t he processes to get t he

o t he r RDLs . T h i s me t ho d c a n b e

Figure 4:

FOWLP RDLs process flow using PECVD and Cu-damascene + CMP.

Figure 5:

Cross section of RDLs using PECVD and

Cu-damascene + CMP.

Figure 6:

FOWLP RDLs process flow for hybrid-RDLs.

Figure 3:

Cross section of FOWLP RDLs using

photosensitive polymer and ECD Cu + etching.