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13

Chip Scale Review May • June • 2018

[ChipScaleReview.com]

appl ied t o FOWLP wit h ch ip -f i r st

and chip-last processing. The RDLs

made by PECVD and Cu-damascene

+ CMP are called inorganic RDLs.

FOWLP RDLs by hybr id-RDL .

As of today, this hybrid-RDL method

on ly appl ie s t o ch ip -la st or RDL -

first, i.e., wafer bumping and chip-to-

wafer bonding are necessary. The key

process steps for chip-last by hybrid

RDLs are shown in

Figure 6

. It can

be seen that a glass carrier-1 is coated

with a sacrif icial layer (

Figure 6a

).

The cont act pad and the f i rst RDL

(RDL1) a re t hen fabr icat ed by t he

PECVD for the SiO

2

dielectric layer

and dual Cu-damascene + CMP for

the conductor layer (

Figure 6b

). The

remaining RDLs are fabricated by the

ordinar y polymer (or photosensitive

polymer) and Cu-plati ng + etchi ng

met hod . Anot he r ca r r ie r-2 is t hen

a t t a ch e d t o t h e o t h e r s i d e of t h e

reconstituted wafer (

Figure 6c

). That

step is followed by debonding of the

c a r r ie r-1 a s shown i n

F i gur e 6d

.

That, in turn, is followed by f luxing,

ch i p - t o -wa fe r bond i ng , cl e a n i ng ,

u n d e r f i l l d i s p e n s i n g a n d c u r i n g

a s shown i n

F i gure 6e

. Then , t he

reconstit uted wafer is molded with

EMC (epoxy molding compound) by

the compression method (

Figure 6f

).

Next comes debonding of the carrier-2

and solder ball mounting as shown in

Figure 6g

.

Figure 7

shows the cross

section of a FOWLP with hybrid RDLs

published by SPIL in ECTC2016 [6].

Figure 8

shows the cross section of a

FOWLP with hybrid RDLs published

by Amkor i n ECTC2017 [7,8]. The

two cross sections are very similar.

FOPLP RDL methods

The re a re also fou r met hod s for

fabr icat i ng RDLs u sed i n FOPLP;

they are discussed below.

FOPLP RDL s by PCB + SAP.

The structure of J-Devices’ WFOP™

i s s h ow n i n

F i g u r e 9

. I t c a n b e

s e e n t h a t t h e r e i s n o t a n EMC .

However, t he re is a met al plate to

s u p p o r t t h e wh o l e p a c k a g e . T h e

RDLs a r e f ab r ica t ed by a p r i nt ed

c i r c u i t b o a r d ( PCB) t e c h n o l o g y

using a semi-additive process (SAP)

[9 -11] . F i r s t , t h e KGD i s p l a c e d

f a c e - up wit h a d he sive on a me t a l

p a n e l c a r r i e r (32 0mm x 32 0mm)

(

F i gure 10

). Then , phot osen sit ive

resin is coated (as the dielectric layer

of the RDL) on top of the KGDs on

the whole panel. This is followed by

Figure 8:

Amkor’s cross sections of hybrid RDLs.

Figure 9:

J-Devices’ WFOP.

Figure 7:

SPIL’s cross sections of hybrid RDLs.