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Chip Scale Review May • June • 2018



May • June 2018

Volume 22, Number 3

Advanced packaging techniques like FOWLP

demand mature lithography solutions for the

challenging processes required to manufacture

high-performance devices. The Veeco-Ultratech

AP300®, which was used for the research in

the featured article, has a variable numerical

aperture lens that can be optimized to maximize

depth of focus while maintaining higher

resolution performance. It can process wafers

with up to 7mm of warpage and is configurable

with an optical system that provides a full wafer

topography map to help optimize the focus

position for each exposure.

Cover photo courtesy of Veeco Instruments Inc.

29 54 International Directory of Test & Burn-in Socket Manufacturers Industry News


7 Creating 1µm RDL structures for fan-out wafer-level packaging Warren W. Flack Veeco Instruments Inc. and John Slabbekoorn imec 11 8 ways to make RDLs for FOW/PLP John H. Lau ASM Pacific Technology Ltd. 20 A closer look into sub-micron die placement: Cpk and Cmk David R. Halk ASM AMICRA Microtechnologies GmbH 25 Thermal cycling of IC devices Ila Pal Ironwood Electronics 39 Sequential-3D integration for advanced semiconductor scaling Anne Vandooren, Jacopo Franco, Arindam Mallik, Liesbeth Witters, Nadine Collaert imec 44 Biodegradable and recyclable materials in semiconductor packaging Randy H.Y. Lo, Andrea S. Chen Siliconware USA, Inc. 50 Challenges of flip-chip MEMS microphones: from state-of-the-art to small housing sizes Sebastian Walser, Anton Leidl, Wolfgang Pahl EPCOS, a TDK Group Company