Previous Page  41 / 60 Next Page
Information
Show Menu
Previous Page 41 / 60 Next Page
Page Background

39

Chip Scale Review May • June • 2018

[ChipScaleReview.com]

Sequential-3D integration for advanced

semiconductor scaling

By Anne Vandooren, Jacopo Franco, Arindam Mallik, Liesbeth Witters, Nadine Collaert

[imec]

echnology innovations are

expected to allow traditional

Mo o r e’s Law s c a l i ng t o

continue for at least five to ten years. At

the same time, researchers worldwide

are exploring alter native options to

overcome a number of challenges –

physical, technological and economical –

associated with further scaling of CMOS

transistor dimensions. One of these

alternatives is sequential-3D integration

(S3D), a relatively new technology that

promises to alleviate problems in classical

2D CMOS (

Figure 1

). This integration

technique involves the vertical integration

of sequentially processed device layers,

and comes in three different f lavors –

depending on where the partitioning and

stacking takes place. First, in transistor-

level S3D, the CMOS gate is split into tiers

of pMOS and nMOS. Second, in CMOS-

level S3D, conventional 2D standard cells

are placed in different tiers. And finally,

the partitioning can be done at the IP block

level to separate, for example, the analog

and I/O functionality from the logic and

memory part. This is referred to as hybrid

S3D (or heterogeneous S3D) (

Figure 2

)

where besides CMOS devices, different

flavors of technologies can be combined.

S3D c ome s w i t h i t s own s e t of

technology challenges, which are further

discussed in this article. When these

challenges can be overcome, the technique

is expected to further enhance device

density per chip area, reduce the length

of the interconnection lines, and facilitate

the co-integration of heterogeneous device

technologies. However, to quantify the real

benefits in terms of power, performance,

area and cost, a systematic investigation

is required for each of the S3D flavors. In

this article, the benefits of the integration

technology are evaluated using advanced

technology nodes, i.e., 5nm and beyond.

Thermal budget: a key technology

challenge

In general, the processing of S3D

integrated circuits consists of three

different blocks (

Figure 3

). The first

block involves standard bottom tier

device processing, up to a certain level

of interconnects. In a second block, a

blanket semiconductor layer needs to be

created on top of the processed device and

interconnect layers. At imec, this is done

by layer transfer based on a dielectric-to-

dielectric wafer bonding technique and a

donor silicon-on-insulator (SOI) wafer. The

third block is the top device processing,

during which the first patterned layer is

aligned to the last processed (interconnect)

layer at the bottom tier level.

D u r i n g s t a n d a r d MOS d e v i c e

processing, various thermal steps are

applied, some of them exceeding 1000°C,

and this presents some major technological

T

Figure 1:

A sequential-3D a) at transistor level, and b)

at cell level.

Figure 2:

Illustration of the hybrid S3D technology. In this example, the logic and memory part is scaled to

the 3nm (or iN5) node in the bottom tier, and the remaining part (analog and I/O) is manufactured at the 28nm

technology node in the top tier. In this particular case, the non-scalable analog and I/O part takes up to 30% of

the overall circuit area.

Figure 3:

Schematic of an envisioned 3D sequential integration flow. After thinning the top Si layer, top-tier

devices can be fabricated in a low thermal budget flow.