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Chip Scale Review May • June • 2018


challenges. On the one hand, to avoid

degradation of the bottom tier devices, the

thermal budget for the top-tier processing

needs to be limited, and this may induce

a mismatch in performance between

the two tiers. On the other hand, the

materials used in some critical process

steps for the bottom tier device (such as

the interconnect metals, device contacts

and gate stacks) need to be sufficiently

thermally stable as to withstand the

(limited) thermal budget required for top

tier fabrication. Furthermore, the thermal

processes may impact the dielectric that

is used for the wafer bonding (

Figure 4


At high temperatures, for example, voids

can be created at the bonding interface.

The dielectric therefore needs to be

sufficiently outgassed prior to bonding,

at a temperature equivalent to the total

thermal budget required for the top

device processing.

A thermally stable metal for the


In view of thermal limitations, the imec

team has investigated metal alternatives to

copper (Cu) for routing at the bottom layer.

These interconnect metals must have both

a good thermal stability to withstand top

device processing, and a low resistance to

maintain a low RC delay. Cu, for example,

has a low thermal stability (450–500°C). At

higher temperatures, Cu atoms can easily

diffuse into the dielectrics and contaminate

the front-end-of-line devices. Tungsten (W),

on the other hand, has a higher thermal

stability than Cu (up to 600°C), but is less

suited due to its higher resistivity. The team

therefore proposes cobalt (Co) as a bottom

back-end-of-line metal. Co provides a 2

to 3 times lower resistance than W, and a

thermal stability as good as W.

Gate stack and contact optimization

Gate stack challenges are also confronted

with thermal limitations, and therefore,

an alternative approach to gate stack

engineering is proposed. A first challenge

relates to the gate stack of the bottom

device. In contemporary technologies,

industry uses a replacement metal gate

flow. As part of this flow, a dummy gate

is deposited to implement a self-aligned

device fabrication; the dummy gate remains

in place during all the high-temperature

process steps (e.g., junction activation),

and only at the end of the process flow is

it removed and replaced by the real gate

stack. This allows larger flexibility in the

choice of work function metals, without this

Figure 4:

FinFET on FinFET device stacking enabled

on 300mm wafers, featuring wafer-to-wafer bonding

and 14nm FinFET technology.