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Chip Scale Review May • June • 2018


choice being limited by thermal stability

concerns. In a S3D f low, however, the

bottom tier device processing is followed

by the top tier device processing, which can

further affect the stability of the bottom

gate stack. To address this issue, imec has

investigated the thermal stability of various

work function metal stacks, and optimized

them for improved stability.

A second challenge relates to the gate

stack of the top tier device. In industry,

rapid high-temperature annealing steps

(“reliability anneals”) are commonly

applied after gate stack deposition to cure

defects in the dielectric SiO





These defects can trap charge carriers and

deteriorate the device reliability, inducing,

as an example, severe bias temperature

instability (BTI). These high-temperature

“reliability anneals” cannot however, be

used when fabricating the top device layer

to preserve the integrity of the bottom

tier interconnects. Therefore, the team

looked into alternative oxide stacks, which

could offer improved reliability without

requiring a thermal treatment. By careful

engineering, the energy level of the traps

with respect to the Fermi level in the

semiconductor channel, the interaction of

carriers with the traps can be minimized.

This engineering can be realized, e.g.,

by inserting a thin LaSiO


interlayer in

between SiO


and HfO


. With this novel

oxide stack, the team demonstrated

sufficient BTI reliability without resorting

to high-temperature “reliability anneals.”

Contacting the transistor’s source, drain

and gate is traditionally done by using

silicides such as nickel (Ni) silicide. These

silicides, however, typically show a limited

thermal stability of the contact resistivity.

The imec team, therefore, looked into

direct contacting to a metal contact (such

as titanium (Ti)/Ti-nitride), a technique

that is increasingly used within advanced

Fi n FET t e ch nolog ie s. Wit h d i r e c t

contacting, a higher thermal stability is

obtained, giving additional relief on the

thermal budget limitations.

Potential benefits of sequential-3D


Compared to a 2D implementation,

the sequential processing of device layers

promises an enhanced device density per

chip area, and a reduced length of the

interconnection lines. But is it really that

beneficial? Can we, for example, expect a

50% area reduction by stacking devices in

two tiers? What is the impact on the RC

delay? And does it follow the economics of

scaling? To answer these questions, imec

has analyzed and quantified the benefits

in terms of power-performance-area-cost

at 5nm and 3nm technology nodes, for the

three different S3D variations.

Transistor-level and CMOS-level S3D:

limited gains in cost and area scaling.

The acceptance of a technology innovation

by the semiconductor industry is heavily

dependent on the manufacturing cost.

Imec used its cost modeling framework

to quantify the cost – at wafer level and

at die level – for transistor-level and cell-

level S3D. As a main conclusion, almost

no cost reduction is obtained compared

to the t raditional 2D 5nm and 3nm

implementations. This is mainly due to

extra process steps, such as additional steps

in the layer transfer, that significantly add to

the manufacturing cost. Also, depending on

the implementation, some of the modules

(such as gate patterning) would have to be

performed twice, and this considerably

adds to the processing cost of the dies.

Moreover, the gain in terms of area

reduction is found to be less favorable for

a S3D implementation compared to a 2D

scaling scenario (

Figure 5

). In traditional

scaling, the primary target is a 50% area

shrink for both logic and SRAM bit cells.

Typically, to achieve a 50% gain, a number

of scaling boosters are applied, such as

a reduction of the number of tracks (i.e.,

the number of middle layers within the

standard cell). For example, to transition

from the 5nm node to the 3nm node,

the number of tracks is reduced from 6

tracks to 5 or 4 tracks. In order to have a

comparable 50% area benefit with S3D for

the 5nm node, only a very limited number

of tracks (2 – 2.5) would be suitable. There

is, however, a fundamental limit to the

minimum number of tracks required for cell

fabrication: at least 3 to 4 tracks are needed

in order to interconnect the transistors

(drain/source and gate/gate), and deliver

power to the transistors. Consequently, due

to the required track resource, an area gain

of 50% is not feasible for the transistor- and

cell-level S3D.

The imec team also investigated the

benefits in terms of RC delay. When scaling

continues, the resistance-capacitance

product (RC) of the interconnect system

strongly increases on account of the

reduced cross section of the wires. It can be

Figure 5:

a) Logic cell layout (ND2 cell) in (left)

traditional 2D and (right) transistor-level S3D

implementation. The figures demonstrate a

representative graphic database system (GDS)

in accordance to 5nm design rules. The top and

bottom tiers are connected to each other through

three types of inter-tier vias. b) Comparison of

the area gain in 2D and transistor-level S3D

implementations. iN7-2D and iN5-2D are 5nm and

3nm 2D implementations, respectively.

Figure 6:

Die cost for different S3D variations. iN7-2D and iN5-2D are 5nm and 3nm 2D implementations,

respectively; T-S3D, C-S3D and H-S3D are sequential-3D implementations at the transistor, cell and IP

block level, respectively.