Chip Scale Review - May June 2018

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42 Chip Scale Review May • June • 2018
expected that stacking transistors or cells
brings some benefits, as the cross section
of the wires can be relaxed to some extent.
The cell-level S3D case indeed turns out
beneficial in terms of RC delay, but the
results very much depend on the process
assumptions. For example, when the top
tier is as performant as the bottom tier, and
the metallization between the two tiers
is in Cu, a 25% reduction in RC delay is
expected for the S3D case compared with
a 2D implementation. When, however,
the top tier performs less than the bottom
tier due to process restrictions, and W,
which is more resistive, is used between
the two tiers, the reduction in RC delay is
smaller. For example, a 15% reduction in
RC delay is obtained when the top tier has
about 20% lower drive compared to the
bottom tier.
The results of the analysis very much
depend on the process assumptions and the
technology nodes considered in the study.
For example, in this study, the technology
is assumed to be mainly front-end-of-
line dominated, i.e., its performance is
still heavily dependent on the parasitics
in the device front end. However, with
further scaling, technology might become
more back-end-of-line dominated, with
increasingly larger RC delay limiting the
overall performance. In this case, because
of gains in RC delay, S3D integration at the
transistor level and cell level might turn out
to be more beneficial.
Hybrid S3D: true benefits. True benefits
are found for a hybrid S3D case, where the
logic and memory part is scaled to the 3nm
node in the bottom tier, and the remaining
part (analog and I/O) is assumed to be
manufactured in the 28nm technology node
in the top tier (Figure 6). In this particular
case, the non-scalable analog and I/O part
takes up to 30% of the overall circuit area
(see also Figure 2).
Despite a considerable increase in wafer
cost, a 33% reduction in die cost compared
to a 5nm 2D system-on-chip (SoC)
implementation (with 125mm2 die size) has
been estimated. This can be understood as
follows. In a traditional 2D implementation,
all devices of the circuit need to be
fabricated and optimized in the same
advanced technology (e.g., 5nm FinFET
technology). With hybrid S3D, the analog
and I/O part can now be moved to a separate
tier and fabricated with older technologies
(28nm, in this case). This clearly makes the
processing less complex and costly. The
same holds for the interconnect schemes.
The wiring that interconnects the transistors
of the scalable parts can be optimized
separately from the interconnects within the
other tier, and the connection between them
can be realized through a regular, dense
interconnect scheme.
It should be noted that the resulting
gains largely depend on the relative
amount of the scalable vs. the non-scalable
part. For example, the effective area
reduction depends on the area of the largest
component. In general, the smaller the non-
scalable part, the smaller the overall benefit
of the hybrid S3D implementation.
Through-Si-via-like processes: a
brief comparison
Sequential-3D integration and through-
Si-via (TSV)-like processes involve
different technologies. TSV-like processes
are used, for example, in 3D stacked ICs.
As an example, these are realized through