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43

Chip Scale Review May • June • 2018

[ChipScaleReview.com]

die-to-wafer stacking, and dies are interconnected using TSVs and

microbumps. S3D, on the other hand, relies on sequential processes and

layer transfer processes. In S3D, the alignment of transistors or cells is

not defined by wafer alignment, but by lithography. As a consequence,

S3D allows achieving smaller contact pitches (a few 100nm) as

compared to TSV-like processing – where the diameter of the TSVs

cannot be scaled below a certain limit. Therefore, S3D will provide the

most benefit when a large number of interconnections between two sub-

systems is required. Overall, the final decision will very much depend

on the circuit and the envisaged application. A typical application of

a S3D implementation can be stacked SRAM cells, where transistors

of neighboring cells are stacked on top of each other. The hybrid S3D

approach will benefit the implementation of next-generation application

hardware such as 5G and machine learning.

Summary

Sequential-3D integration (S3D) is perceived as a promising

alternative to continue the benefits offered by semiconductor scaling.

This integration technique involves the vertical integration of

sequentially processed device layers, and comes in three different

flavors – depending on where the partitioning and stacking takes

place. In this article we have reviewed some of the solutions proposed

by imec to tackle the technology integration challenges. Also, the

benefits of the technology have been quantified through a power-

performance-area-cost analysis. As a main conclusion, the largest

benefit is found for a heterogenous S3D case, where the logic and

memory part is using a scaled technology, and the remaining non-

scalable part (analog in combination with I/O) is manufactured in a

more relaxed 28nm technology in the top tier. S3D is found to be less

straightforward for dimensional scaling (i.e., S3D at transistor or cell

level). The relative benefits are largely dependent on the technology

assumptions and on the component distribution.

Acknowledgement

These results have been presented at the 2017 IEDM conference,

within the paper, “The impact of sequential-3D integration on the

semiconductor scaling roadmap,” by A. Mallik, et al.

Biographies

Anne Vandooren received her MS in Electrical Engineering

f r om t he U. Ca t hol ique de Louva i n ( UCL), Belg ium,

and he r PhD i n Elect r ical Eng i nee r i ng f rom t he U. of

California, Davis. She is a Senior Researcher at imec; email

Anne.Vandooren@imec.be

Jacopo Franco received BSc and MSc degrees in Electronic

Engineering from the U. of Calabria, Italy, and a PhD degree in

Electrical Engineering from KU Leuven, Belgium. He is a Principal

Member of Technical Staff in the device reliability group at imec.

Arindam Mallik received his MS and PhD degrees in Electrical

Engineering and Computer Science from Northwestern U. He is

the Project Leader for imec’s Machine Learning Program, focusing

on technology innovation needed for optimum performance of

Machine Learning/Artificial Intelligence platforms.

Liesbeth Witters received the BSc and MSc degrees in

Chemical Engineering from KU Leuven, Belgium and ENSPM,

Paris, France, respectively. She is a Principal Member of the

Technical Staff at imec.

Nadine Collaert received MS and PhD degrees in Electrical

Engineering from the ESAT Department, KU Leuven, Belgium.

She is a Distinguished Member of Technical Staff at imec.