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37

Chip Scale Review May • June • 2019

[ChipScaleReview.com]

his paper describes the benefits

and the money savings by

combining the system-level test

(SLT) and burn-in (BI) steps for automotive

system-on-chip (SoC) devices. Moreover,

the paper suggests the requirements to

merge SLT and BI. In this way, SLT can

detect faults that can be excited only

functionally, for example in the logic of

power-on self-test. Moreover, BI brings

the device under test (DUT) in the worst

possible condition by means of the climatic

chamber. This allows one to check the

correctness of the DUT’s behavior (using the

SLT) under the worst condition compared to

the application condition (by means of BI).

In addition, the SLT equipment can control

the design for testability (DfT) structure

of the DUT. In this perspective, the goal is

to reduce the tests performed by the final

test (FT) automatic test equipment (ATE),

thereby reducing test time and cost. The

proposed approach is affordable only with

the BI time reduction with high-voltage,

which is described in [1].

Background

This section provides the reader with the

required information about system-level test

and burn-in flow.

S y s t em - l e v e l t e s t .

SLT o f t e n

complements the other steps of a test flow,

which include wafer sort, BI, and FT,

using functional test. The functional test

complements the structural test because it

covers some defects that structural testing

does not detect. For example, the functional

test works at the system operational

speed, while some DfT techniques do not.

Moreover, SLT exercises the system exactly

in the same conditions as the operational

phase [2].

SLT is sometimes used as an effective

method to lower the defectivity, often

measured in terms of defective parts per

million (DPPM). SLT increases the quality

of the shipped products, which is crucial for

safety-critical applications. SLT addresses

both defects and marginalities [3]. In our

view, a possible defect (physical) is always

present, and test conditions may only change

the set of visible symptoms. Conversely, a

marginality (behavioral) may not be present

in a subset of possible test conditions, and

may impact the functionality under specific

process, voltage, and temperature (PVT)

condition(s), only. A marginality might also

be active only after a specific functional

sequence (including software) is applied.

Detection of marginalities have always been

delegated to bench-top validation, under the

assumption that a reduced number of corner

cases are enough to view the symptoms of

all marginalities.

Moreover, the inherent limits of optical

lithography and process variation control in

deep-nanometer manufacturing are creating

more subtle defect types that cause failures

only under certain system operating (voltage,

temperature) conditions and workloads [4].

Production test running on ATE is unlikely

to cover all failing conditions to expose such

so-called marginal defects. Even though

area scaling continues, the end of Dennard

voltage scaling has brought power and

thermal reductions to the forefront as the

key design challenges in the era of mobile

computing. Complex power management

schemes orchestrated by energy-aware

scheduling software are now the norm in

multi-core system-on-chip (SoC) devices.

With shrinking voltage margins, supply grid

noise and activity-dependent local aging

can push weak devices below safe operating

thresholds and trigger failures [5].

In the following, we report a list of cases

(from the literature) that are addressed by

functional test and not by the structural test:

1. Complex clock and power domain

interactions controlled by embedded

software [6].

2. Fu nc t iona l i nt e r a c t ion s a s t he

operating system boots [6].

3. Under certain application scenarios

where memory is accessed at a high

rate, read/write soft data errors can

occur, on account of local workload-

dependent aging or activity-induced

supply droop and cross-talk [7].

4. Complex protocols are increasingly

being implemented in hardware.

These protocols cannot be tested in

isolation by structural test [8], e.g., a

bus at its maximum bandwidth.

5. Hardware resource management, such

as dynamic system re-configuration [8].

6. Exercising central processing units

(CPUs) with extreme work loads,

stress architectural specific operations

such as multithread, floating-point

units, maximum concurrent operations

on multiple threads and cores, TLB

hit/miss, caches and its tag-RAM,

pipeline exerciser [8].

Some further defects are targeted by the

SLT solution, which are specific to new

automotive devices, e.g., to consider the

environment in which they are expected to

work [9].

Burn-in flow.

The main purpose of BI is

activating those latent defects not observable

during wafer sort and package test activities

at time zero. During BI, we increase

temperature to reach a possibly stable and

high value with respect to the maximum

allowed junction temperature of the device.

Supply voltage is elevated to complete the

stress concept. In previous works [10-13]

we discussed advances regarding BI. We

aimed to maximize the quality of stress and

reduce the cost for optimizing this stage by

interleaving the stress phases with the test.

Because of its relatively long test duration,

system-level test represents a cost challenge

if purely considered as an additive stage to

existing test flows. BI or test during burn-

in (TDBI) stages permit a relatively cost

efficient solution to manage very long test

times. However, there are several technical

obstacles that complicate the merging of

these two methods. The rest of the paper

analyzes these obstacles and proposes some

T

Effective screening of automotive SoCs by combining

burn-in and system-level test

By P. Bernardi, D. Calabrese, M. Restifo, F. Almeida, M. Sonza Reorda

[Politecnico di Torino]

and D. Appello, G. Pollaccia, V.

Tancorre, R. Ugioli, G. Zoppi

[STMicroelectronics Srl]