Previous Page  41 / 68 Next Page
Information
Show Menu
Previous Page 41 / 68 Next Page
Page Background

39

Chip Scale Review May • June • 2019

[ChipScaleReview.com]

responses at the same time. Common BIBs have a limited number of

resources, so it is necessary to change the architecture of the BIB to

enable SLT.

The proposed test flow moves the total control from a central ATE

to a workstation (as a simple host PC), which orchestrates the smart

and improved BIBs.

Figure 3

depicts the new architecture of the BIB,

which maintains the same parallelism of the common SLT. In this

case, the parallelism is no more on the DUTs, but it is on SLT units.

A SLT unit is composed of two different boards:

1. A controller board, which interacts with the BI tester and

transforms the high-level commands into low-level instructions

and values to be applied to the DUT. The controller board is

also in charge of receiving the output values produced by the

DUT, analyzing them and conveying the results of the test to

the BI tester. The control board is equipped with a variety of

components. A microprocessor manages all the SLT steps,

and an eNVM and RAM module support the microprocessor.

The general connectivity module implements all the possible

communication interfaces such as I2C, serial peripheral

interface (SPI), Ethernet, controller area network (CAN), etc.

Moreover, the voltage regulator and the power supply enable

a telemetry feature allowing a fine-grain tune of the supply

voltage to the DUT.

2. A device board, which includes the socket where the DUT

is loaded and all the other IPs required for an efficient and

exhaustive SLT. The device board directly hosts and interacts

with the DUT using additional interfaces. Hence, the device

board is equipped with the required number of interfaces

Figure 2:

Structure of a common burn-in board.

Figure 3:

Structure of a new burn-in board to enable SLT.