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Chip Scale Review May • June • 2019


to the control board with an acknowledge

message, the loading process ends with

success. If the watchdog timer WLOAD

expires, the control board turns off the

power supply of the DUT, thereby moving

the system to a safe state.

After the test suite loading, the control

board triggers the execution of the test

suite. Then, the control boards initialize a

watchdog timer “WLIFE” for checking if

the device is still alive. If the device replies

with a life message, the watchdog timer

restarts. If the watchdog timer WLIFE

expires, it means that the DUT is not

behaving correctly, the control board aborts

the test suite and restarts the test suite. If the

DUT continues not to behave as expected

after the reset, the control board turns off

the power supply moving the system to

a safe state. Finally, if the DUT executes

the test suite correctly, the control boards

download the test suite results.

The interface for implementing the

protocols can be implemented with a

software command interface, which

is built upon UART. This interface is

usually present on all SoCs and allows

attainment of the necessary speed for the

actual desired purpose. It is also possible

to transfer data in parallel with the CPU

activity. An additional feature, a real-

time kernel operating system, provides

independent threads useful for real-time

applications and, therefore, it is necessary

to test their responses.

Protocol for enabling structural tests.

The proposed BIB also allows running a

structural test using the JTAG interface of

the DUT. This section describes a protocol

that enables the TAP interface by means of

interfaces equipping the control board.

The control board uses at least two SPI

interfaces (a master SPI, which controls

a slave SPI, plus the JTAG) and some

general purpose input/outputs (GPIOs)

inside its general connectivity module for

establishing a communication with the

TAP interface through the JTAG connector.

Figure 5

shows details about the connection

between the control board and the DUT.

Managing a TAP controller requires

commanding at least the TMS and TCK

signals (TRST is optional). The TMS

signal is connected to the MOSI signal

of the first SPI, while TCK is in short

circuit with the SCLK signals of both

SPIs. This configuration permits the

evolution of the state inside the finite state

machine (FSM) implemented by the TAP

controller. Managing a boundary scan

is mounted on top of the control board. The

control board is fixed for all the DUTs and

reusable, while the device board changes

when testing a different DUT family.

Typically, the device board and control

board are stacked one over the other.

Protocol for enabling functional tests.

The BIB architecture requires a special

purpose protocol for triggering a functional

test suite and the access to the TAP

controller. The proposed protocols enable

the ATPG, the functional test, the BIST

phase used in the common dynamic BI, and

the functional test used for SLT.

Figure 4

shows the test protocol

implemented for running a functional

test suite in the SLT environment. First,

the controller board loads the test suite

inside the memory of the DUT. Then, the

controller board initializes a watchdog

timer “WLOAD” for monitoring the correct

load of the test suite. If the DUT replies

that are necessary for testing the

device connectivit y. Moreover,

the device board is equipped with

internet protocols (IPs), which are

necessary to functionally use the

system to be tested. Some memory

may be required to store the low-

level stimuli to be applied to the

DUT, and the values to be compared

with those it produces and to support

the DUT boot. Finally, a f ield-

programmable gate array (FPGA)

device may sometimes be present to

act as a programmable switch-matrix

interfacing the DUT data channels

with those of the controller board.

The device board is specific to the DUT

product that is currently being tested,

while the controller board is designed to be

highly versatile so as to be compliant with a

broader range of products. The device board

Figure 4:

Protocol for enabling a functional test suite in an SLT environment.

Figure 5:

Protocol for enabling a structural test inside an SLT environment.