Chip Scale Review May • June • 2019[ChipScaleReview.com]
needs to also control TDI and TDO. TDI
is connected to the MOSI of the second
SPI, while TDO is connected to the MISO
of the first SPI. The JTAG interface can
require an additional signal, for example
an asynchronous reset, which is called
JCOM. These kinds of signals can be
controlled using common GPIOs.
Th is is t he mi n imal protocol for
accessing a standard TAP. The protocol
cont r ol s t he s t a t e i n side t he TAP
controller, loads instructions inside the
TAP register, downloads results of TAP
instructions and uses the DUT scan chain.
If the structural test requires additional
signals, the protocol can be enhanced with
further SPI interfaces.
The proposed approach has been
u s e d f o r t e s t i ng a SoC , wh i ch i s
based on a 40nm CMOS technology
microcontroller by STMicroelectronics,
which serves automotive applications.
The DUT is safet y- compliant wit h
t he ISO -26262  up t o ASI L -D
applications. Inside the DUT there is
a microcontroller with embedded non-
volatile memory (i.e., a MCU).
This product undergoes severe test
requirements to reach very low DPPM
f igu res. Especially begi nni ng with
the 40nm node, these devices reached
a r el a t ively h ig h complex it y. The
complexity depends on a combination
of factors, i ncludi ng the relat ively
large number of integ rated IPs and
the possibility of IP reconfiguration
offered by the non-volatile memory.
The widest possible ver if ication of
configurations is a main goal for the
applicative test. To implement this
objective, we def ined an applicative
setup with the minimum possible set of
components, for the obvious objective of
minimizing the board space occupation.
Space occupation is a key parameter
determinant in the cost of test because
it directly influences the test parallelism
for a given board space.
The additional key factors driving test
costs are typically the test duration, the
number of stages (e.g., a stage requires the
DUT to be handled and put in a socket for
the test), the parallelism, the throughput
ratio, and the cost of the equipment. In
our analysis we did not consider other
factors, which are independent from our
project scope, such as the efficiency and
the electrical yield.
gives some figures used to
compute the test costs per device without
the proposed methodology, i.e., with a
solution where BI and SLT are applied
Traditional burn-in operations, usually
characterized by off-line automation, give
better cost efficiency with relatively longer
durations. In this case, to load devices to
the sockets on the board, an equipment is
shared between multiple burn-in testers,
named automated loader/unloader (ALU).
The board movement from the ALU to
the BI tester may happen either manually
or by robots depending on the level of the
automation. These off-line operations add
an overhead time to the electrical burn-in
time and an extra cost.
presents the test costs per
device per minute with the proposed
approach. This methodology will be
referenced as BI&SLT. Our analysis doesP RoHS