Chip Scale Review May • June • 2019[ChipScaleReview.com]
not account for the utilization efficiency, which we considered the
same for each equipment. Our work aims at enabling the technical
conditions to maintain the best possible cost effectiveness of
the test flow during its entire lifecycle. In the early phases, with
relatively high defectivity and consequent long time for the
screening of early-life fails, the adoption of a flow with both
BI&SLT is economically affordable. In these phases, you should
also expect relatively low manufacturing volumes.
shows that a cost tradeoff exists between the BI&SLT and BI+SLT
approaches depending on the BI time. It is possible to combine
BI and SLT duration such that the possibility of combining them
together becomes economically convenient.
the time axis represents the effective burn-in time
without the additional time for load/unload operations. Conversely,
the time for the BI+SLT approach accounts also for the extra time
for the load/unload operations, because it is required intrinsically
by the approach, while the time for the BI&SLT methodology is
only the BI time.
The proposed strategy becomes even more convenient when
exploiting the high-voltage stress for exponentially reducing the
BI time, as described in . Using high voltages in BI reduces
dramatically the DPPM even with a short BI time duration.
The proposed flow has its maximum saving when the BI time is
lower than 10-12min. In addition, it is also important to remark on
the existence of mechanical effects at each stage. Each time parts are
handled, there is the probability of a mechanical damage to leads/balls
and/or to the package body. The reduction in the number of stages,
Test costs per device without the proposed methodology.
Test costs per device with the proposed methodology. For footnote a, refer
to Table 1.