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Chip Scale Review May • June • 2019


therefore, benefits the final mechanical

yield, which in our experience, may account

for a fraction of a percent. This apparent

small number is instead very relevant with

the economy of scale and a function of the

device bill of material (BOM) cost.


This paper introduces and illustrates a

new approach for combining the BI and

SLT steps, which are today commonly

used when dealing with ICs used in safety-

critical applications. Possible scenarios for

a stress parallelization are analyzed and

investigated. The approach guarantees

complete parallelization of the two test

steps exploiting a new architecture that

mixes the benefits of both BI and SLT,

thereby implementing a better screening

while reducing the whole cost.

The solution is oriented to devices

with a low-power consumption like the

MCU test case which is controlled in

temperature by passive systems. There is

also the possibility for reducing the cost

of the following final test tasks to the

adoption of the proposed approach. This

topic will be investigated in future works.


1. M. F. Zakaria, et al., “Reducing

burn-in time through high-voltage

stress test and Weibull statistical

analysis,” IEEE Design & Test of

Computers, vol. 23, no. 2, pp. 88-

98, March-April 2006.

2. A. Ju t ma n , M. S . Re o r d a , H.

Wu n d e r l i c h , “ H i g h - q u a l i t y

system-level test and diagnosis,”

IEEE 23rd Asian Test Symp., 2014,

pp. 298-305.

3. J-J. Liou, M-T. Hsieh, J-F. Cherng,

H. H. Chen, “Cost reduction of

system-level tests with stressed

structural tests and SVM,” 2015

IFIP/IEEE Inter. Conf. on Very

Large Scale Integration (VLSI-SoC)

4. P. G. Ryan, et al., “Process defect

trends and strategic test gaps,”

IEEE Inter. Test Conf., 2014.

5. H . A m r o u c h , e t a l . ,

“Interdependencies of degradation

e f f e c t s a n d t h e i r i mp a c t o n

computing,” IEEE Design & Test,

vol. 34, no. 3, pp. 59-67, June 2017.

6. H. H. Chen, “Beyond structural

test, the rising need for system-

level test,” 2018 IEEE Inter. Symp.

on VLSI Design, Automation and

Test (VLSI-DAT), 2018, pp. 1-4.

7. B. Eklow, “On Microprocessor

Re l i a b i l i t y,” I EEE Compu t e r

Society, Computing Now, 2013,

[online video] Available: https://

8. P. Agga r wa l , “Co s t- ef fe c t ive

manufacturing test using mission

mode t e st s ,” I EEE I nt e r. Te st

Conf., 2007.

9. D. Appello, “Testing of automotive

e l e c t r o n i c I C s ”,

Ch i p S c a l e


, Nov/Dec, 2017.

10. P. Bernardi, et al., “A DMA and

CACHE - b a s e d s t r e s s s chema

f o r b u r n - i n o f a u t o m o t i v e

microcontroller,” 18th IEEE Latin

Amer. Test Symp. (LATS), 2017,

pp. 1-6.

11. D . A p p e l l o , e t a l . , “ A

c omp r e h e n s i ve me t h o d o l og y

for stress procedures evaluation

a n d c omp a r i s o n f o r b u r n - i n

of au t omo t i ve SoC ,” De s ig n ,

Aut omat ion & Te st i n Eu rope

Conference & Exhibition (DATE),

2017, pp. 646-649.

12. D. Appello, et al., “An optimized

test during burn-in for automotive

SoC,” IEEE Design & Test, vol.

35, no. 3, pp. 46-53, June 2018.

13. D. Appello, et al., “An evolutionary

a lgo r i t hm a pp r oa ch t o s t r e s s

program generation during burn-

in,” Jour. of low-power electronics,

Mar. 2018, pp. 86-98.

14. ISO 26262-[1-10], Road vehicles –

Functional safety, 2011.


Paolo Bernardi (MS’02 and PhD’06 in Computer Science) is an Associate Professor of the Politecnico di

Torino U., where he works in the Electronic CAD and Reliability research group. His current interests include

system-on-chip test and reliability, especially in the area of high-quality automotive devices. Prof. Bernardi is

a member of the IEEE and currently acting as the General Chair of the Test Technology Educational Program

(TTEP) and the Program Chair of the Automotive Reliability and Test (ART) Workshop. He was recently

acting as Topic Chair for several IEEE conferences and he published more than 120 scientific papers.

Davide Appello is Director of Product Engineering at the Automotive Digital Products division of STMicroelectronics Srl,

Agrate Brianza, Italy. He is in charge of managing all industrialization activities (probe and package) for all ranges of digital

products for automotive including MCUs with embedded non-volatile memories, devices for infotainment, and ADAS. He

earned a degree in Electronic Engineering from the “Alma Ticinensis Universitas” of Pavia in Italy. He is also active with

IEEE-TTTC and is vice-chair of the automotive and reliability test workshop (ART) and on the program committee of several

conferences including ETS and DATE. He has published more than 80 papers for various conferences and magazines.

Figure 6:

Trade-off between BI&SLT and BI+SLT approaches.