Chip Scale Review May • June • 2019[ChipScaleReview.com]
therefore, benefits the final mechanical
yield, which in our experience, may account
for a fraction of a percent. This apparent
small number is instead very relevant with
the economy of scale and a function of the
device bill of material (BOM) cost.
This paper introduces and illustrates a
new approach for combining the BI and
SLT steps, which are today commonly
used when dealing with ICs used in safety-
critical applications. Possible scenarios for
a stress parallelization are analyzed and
investigated. The approach guarantees
complete parallelization of the two test
steps exploiting a new architecture that
mixes the benefits of both BI and SLT,
thereby implementing a better screening
while reducing the whole cost.
The solution is oriented to devices
with a low-power consumption like the
MCU test case which is controlled in
temperature by passive systems. There is
also the possibility for reducing the cost
of the following final test tasks to the
adoption of the proposed approach. This
topic will be investigated in future works.
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Paolo Bernardi (MS’02 and PhD’06 in Computer Science) is an Associate Professor of the Politecnico di
Torino U., where he works in the Electronic CAD and Reliability research group. His current interests include
system-on-chip test and reliability, especially in the area of high-quality automotive devices. Prof. Bernardi is
a member of the IEEE and currently acting as the General Chair of the Test Technology Educational Program
(TTEP) and the Program Chair of the Automotive Reliability and Test (ART) Workshop. He was recently
acting as Topic Chair for several IEEE conferences and he published more than 120 scientific papers.
Davide Appello is Director of Product Engineering at the Automotive Digital Products division of STMicroelectronics Srl,
Agrate Brianza, Italy. He is in charge of managing all industrialization activities (probe and package) for all ranges of digital
products for automotive including MCUs with embedded non-volatile memories, devices for infotainment, and ADAS. He
earned a degree in Electronic Engineering from the “Alma Ticinensis Universitas” of Pavia in Italy. He is also active with
IEEE-TTTC and is vice-chair of the automotive and reliability test workshop (ART) and on the program committee of several
conferences including ETS and DATE. He has published more than 80 papers for various conferences and magazines.
Trade-off between BI&SLT and BI+SLT approaches.