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Chip Scale Review May • June • 2019

[ChipScaleReview.com]

Exposed die fan-out wafer-level packaging

by transfer molding

By Sebastiaan H.M. Kersjes, Jurrian L. J. Zijl, Niels de Jong, Henk Wensink

[Besi Netherlands B.V., The Netherlands]

i t h c o n t i n u o u s

development in packaging

technology, fan-out wafer-

level packaging (FOWLP) has become

an established approach to reach higher

integration levels and geometric efficiency.

Up to now, the FOWLP market has been

mainly focused on compression molding

using relatively thick mold caps, basically

as an outcome from the embedded wafer-

level ball grid array (eWLB) development

star ted by Inf ineon. With the wider

adoption of FOWLP, new encapsulation

processes and equipment have also been

introduced into the market. One such

technology is wafer-level transfer molding.

This technology evolved from the current

FOWLP capabilities, and achieves the

thinnest mold cap possible via a process

called exposed die molding, which can only

be accomplished using transfer molding.

This paper discusses two of the key

factors that are crucial for a successful

transfer molding process of thin 12”

exposed wafer-level packages. First, the

influence of epoxy mold compound (EMC)

on warpage is discussed. Contrary to

compression molding, transfer molding uses

materials that so far tend to induce more

warpage. This paper introduces the basics

behind warpage and how this can be used

to select a proper EMC. Completing this

section is an indicative warpage calculation

using an analytical approach. Second, the

topic of dynamic clamping in correlation

to exposed die molding is discussed. A key

part of exposed die molding is the critical

balance between the clamping force and

the fluid pressure of the injected EMC. The

control strategies used to maintain this

balance will be discussed in this second

section. Finally, an exposed die 12” wafer-

level molded demonstrator is presented.

Introduction

Performing transfer molding on 12”

wafers is something many have thought

to be impossible. The EMC has to flow

through a narrow slit over such a long

distance that it becomes very challenging

for the EMC as well as for the equipment.

Traditional EMC will inhibit a high

viscosity, which leads to a very high

f low resistance. Also, gel times are

often too short to allow enough time for

completely filling of the 12’’ mold cap.

Hence, this process development started

by characterizing the flow behavior of

EMCs, which resulted in the discovery

of varieties that could do the task. This

encouraged the development of actual

equipment, and the pursuit to realize

a repeatable basic wafer-level transfer

molding process. Because there are

many types of applications in wafer-level

packaging, the research continues to have

the best combination of process settings

and material properties. One particularly

challenging application is exposed die

molded underfill (E-MUF) at the wafer

level, for which the schematic process

flow is shown in

Figure 1

.

In the first phase shown in

Figure 1

– “Loading” – a carrier wafer (further

called simply “wafer”) containing flip-

chip devices can be seen where the mold

tool is closed and is gently pressing against

the top surface of the flip chips (die). In

the second phase, the EMC is transferred

through the gap between the top mold tool

and the wafer, thereby encapsulating the

flip chips on five sides. The pressure on

the flip-chip device should be high enough

to prevent EMC from flowing over the flip

chips, but low enough to prevent damage

to the interconnect. In the third and final

phase, the EMC is compacted to eliminate

potential voids and improve adhesion. This

leads to a high EMC fluid pressure, and

the full clamp force has to be applied on

the package, while keeping the resultant

force on the die surface unchanged. This

dynamic clamping behavior needs to be

accurately tailored to the application.

The reason to pursue this path of wafer

transfer molding is to bring something

ext ra to the 12” wafer package. I n

general, the EMC material is available at

a lower cost and has a shorter cure time,

which can boost the throughput. When

performing molded under fill (MUF),

the process of capillary underfill (CUF)

can further be omitted yielding another

cost reduction. Also, because the mold

tool is closed before the injection of

the EMC, parts on the wafer or die can

be kept clean and exposed without an

extra backgrinding step, which gives

new possibilities in packaging strategies

li ke 3D st ack i ng. Fu r t hermore, by

clamping on the die, the die position is

secured and “die swim” is prevented.

Of the many challenges that were faced

during the development of this process,

two are highlighted in this paper. One

refers to the material side and selection

of the EMC that has the least warpage.

The other challenge refers to the force

balance on the mold tool and how this is

maintained in the equipment.

W

Figure 1:

Schematic process flow of the E-MUF

FOWLP process.