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Chip Scale Review May • June • 2019


Improving Si and SiC wafer dicing yields with thermal

laser separation

By Dirk Lewke, Christian Belgardt, Hans-Ulrich Zühlke, Mandy Gebhardt

[3D-Micromac AG]

ncreasing semiconductor content

i n mobile, high-per formance

c ompu t i ng , au t omo t i ve a nd

Internet of Things (IoT) applications is

driving continued growth in demand

for materials such as silicon and silicon

carbide (SiC). Silicon wafer shipments

are expected to continue to reach record

levels through 2021 [1], while the SiC

power device market is expected to grow

from $302 million in 2017 to $1.5 billion

in 2023 [2].

For both silicon and SiC-based devices,

die singulation – dicing the product

wafers into individual dies that are

subsequently packaged – is an essential

process that is critical to product yields.

At this stage, there is no possibility for

rework, and maintaining the integrity

and performance characteristics of the

devices is paramount to fab profitability.

Me c h a n i c a l b l a d e d i c i n g i s t h e

predominant dicing technology in the

semiconductor industry today for both

silicon and SiC die singulation. However,

wit h t he mig r at ion t o la rge r- si zed

substrates and thinner wafers, such as for

3D-IC packaging or for reducing “on”

resistance in vertical power transistors,

mechanical blade dicing is increasingly

ch a l le nge d by c o s t of owne r sh i p,

throughput and yield factors.

I n a p r e v i o u s a r t i c l e [ 3 ] , w e

investigated the yield benefits of applying

a laser dicing approach, known as TLS-

Dicing™ (thermal laser separation), to

SiC wafers, and demonstrated improved

process performance by reducing or

eliminating micro cracks, chipping and

delamination that lead to yield loss. In

this article, we will study the impact of

thermal laser separation on the electrical

performance of singulated SiC devices,

which is a particularly critical metric for

power devices. In addition, we will also

investigate the effects of thermal laser

separation on wafer bending strength for

both SiC and silicon wafers, a crucial

parameter for wafer thinning applications.

Thermal laser separation (TLS)

TLS is a kerf-free laser-based dicing

technology [4]. By performing TLS, a crack

is guided by controlled thermally-induced

mechanical stress using a continuous-wave

laser to locally heat up the material to be

cut along the dicing street. Directly after the

laser-heated zone, a water aerosol quickly

cools down the material (

Figure 1

). This

temperature gradient introduces a tensile

stress capable of running one controlled crack

independent of the lattice plane through the

material. This cleaving process results in high

edge quality without scratches, micro cracks

or chipping, and runs with up to 400mm/s

feed rate. The complete wafer material is fully

separated by one laser pass.

This cleaving is the main principle of

TLS. Nevertheless, TLS is always a two-step

process. The introduced stress field is capable

of guiding a crack, but not introducing a

crack. Therefore, a crack must be introduced

before the cleaving process. This is done by

a scribing process where an initial crack is

introduced in the material to be cut. This

initial scribe involves a very short (less than

300µm long) ablative laser scribe that is

introduced at the beginning of the crack. TLS

with initial scribe is used in the photovoltaic

industry to cut solar cells into two half cells

for half-cell modules. In order to increase

the straightness of the TLS cleaving line,

a continuous scribe can be used. With this

technology, a scribe is performed all along the

line to be cut in order to define the cleaving

position at each point along the cleaving line.

For surface scribes on wafer substrates,

two technologies are used. For SiC wafers,

a continuous surface scribe together with a

technology to remove particles in situ, called

Clean Scribe, can be used. For silicon wafers,

there are higher requirements regarding

particles and breaking strength. Therefore,

a different continuous scribe is needed for

silicon, which is performed beneath the

surface in order to not affect edges of the

dice to be cut. This technology is called

Deep Scribe. Following, these two different

approaches for SiC and Si are explained in

detail and results are shown.

TLS with clean scribe for SiC wafers

SiC is mainly used for power electronic

devices. Main drivers for SiC wafer dicing

are the dicing costs and the throughput.

While mechanical blade dicing is sufficient

for standard power electronic devices on

silicon-based devices, this technology suffers

from high process costs and low throughput

with SiC dicing. These drawbacks are due to

the very high hardness and brittleness of SiC.

However, these material properties make SiC

an optimal candidate for TLS technology.

For example, the TLS feed rates of up to

400mm/s are up to 40 times faster compared

to mechanical blade dicing.

To improve straightness during TLS

processing, a continuous surface scribe is

used for TLS. Additionally, this surface

scribe opens structures (e.g., product control

monitoring structures) inside the dicing

street or metal pads at the wafer edge

region. Nevertheless, with a continuous

surface scribe, particles are generated,

which can subsequently migrate to the

active chip regions and lead to yield loss

during packaging. To minimize the number

of particles without the need for expensive

protective coatings, the clean scribe

technology (patent pending) was developed.

During clean scribe, a water aerosol (similar


Figure 1:

Principle of TLS-Dicing™.