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Chip Scale Review May • June • 2019

[ChipScaleReview.com]

Packaging high-performance memory devices

By Damon Tsai

[Rudolph Technologies, Inc.]

h i l e w i r e b o n d i n g

remains the dominant

technology for chip-to-

package connections, advanced packaging

processes are gaining a growing share of

the market. The transition away from wire

bonding is especially notable in high-

performance memory applications, where

shorter signal paths, higher speed, smaller

form factor and lower power are most

valuable. Significant growth is forecast

for both flip-chip dynamic random access

memory (DRAM) and high-bandwidth

memory (HBM) across a broad range

of applications, with a commensurate

decrease in wire bonding. Flip-chip,

wafer-level packaging (WLP), fan-out

wafer-level packaging (FOWLP), and fan-

out panel-level packaging (FOPLP) are

now seeing increasing adoption. These

advanced packaging methodologies

present unique inspection and metrology

challenges and opportunities, including

through-silicon vias (TSVs), fine-pitch

redistribution layers (RDLs), copper pillar

bumps, micro-bumps and die-level cracks.

Market drivers

Dema nd fo r mo r e f u nc t ion a l it y

in a smaller footprint has driven the

microelectronics industry since it began.

In the context of memory, functionality

refers to dramatic increases in the amount

of data to be stored and the read/write

speeds. In applications such as network

ser ver s, a r t if icial i ntelligence and

machine learning, the need for speed and

the massive volume of data are driving

reductions in size because shorter signal

paths are inherently faster. Graphics

applications require fast, wide connections

between the graphics processing unit

(GPU) and integrated high-bandwidth

m e m o r y ( s t a c k e d DR A M ) . F o r

autonomous driving applications, the

need for speed and capacity is coupled

with increased reliability requirements.

In mobile and wearable applications,

small size is itself a vir tue, but the

coming of 5G will multiply demands for

memory capacity and speed. In all cases,

increasing speed and volume requirements

are also driving increases in the number

and density of I/O connections.

Packaging technologies play a critical

role in determining a device’s ability to

meet performance and size requirements,

which include:

• Wire bonding, where f ine wires

connect pads on the die to pads on

a substrate or to other die within

the package, remains the dominant

interconnect technology. As design

rules shrink, however, wire bonding

struggles to achieve the speed, small

size and I/O density needed for

advanced applications.

• Flip-chip packaging is a mature

technology that reduces package

size, increases I/O densit y, and

increases speed by depositing solder

on pads on the top surface of the

chip and then flipping the chip over

to connect to pads on a substrate.

• A d v a n c e d 2 D a n d 2 . 5 / 3 D

packagi ng processes use f ront-

end-like processes to form external

connections on the chip and come

i n many va r iet ie s. Wafe r-level

processes form the connections

on the wafer before it is cut into

individual die. Fan-out wafer-level

processes separate the die but then

reconstitute them on a wafer-like

substrate, adding space between die

to allow room to redistribute the

connections on the die using a thin

organic substrate. Fan-out panel-

level processes are similar, but the

reconstituted panel is not constrained

to be wafer-like and is both larger

and rectangular.

T hou g h w i r e b ond i ng i s l i ke l y

t o r e t a i n it s domi n a nc e fo r ma ny

mainstream applications, its growth rate

is limited while the share of packages

using flip-chip and advanced packaging

processes is increasing at a faster pace

as a percent age of overall package

growth. Growth in flip-chip packaging

is driven primarily by the transition of

DRAM from wire bond to flip chip. This

is especially true for mobile DRAM

where 5G will make it increasingly

diff icult for manufact urers to meet

performance and cost targets with wire

bond technology. Flip-chip DRAM is

already used in application processors

f r om ma j o r p r ov i d e r s , i n c l u d i n g

Qualcomm, HiSilicon, and Mediatek,

and the transition is expected to expand,

with f lip chip dominating DRAM by

2023. One study [1] projects a compound

annual growth rate (CAGR) of 7.8% for

flip-chip packages from 2017 to 2022.

Demand from smartphones, tablets

and laptops is driving growth in WLP

as well, with CMOS image sensors,

wearables and automotive devices also

contributing. The same study [1] predicts

a CAGR for WLP at 12% from 2017

to 2022, and projects WLP to surpass

flip chip in total number of packages in

2019. Many new applications, including

ba se - ba nd p roce s sor s , appl icat ion

processors, RF transceivers, switches,

power management integrated circuits

( PMIC), I nt e r net of Th i ngs ( IoT),

automotive, sensors, and logic/memory

c omb i n a t i o n s , a r e u s i n g f a n - o u t

packages, and the study also predicts

an aggressive transition from wafer- to

panel-based fan-out processes.

Inspection and metrology for

advanced packaging processes

A l t h o u g h a d v a n c e d p a c k a g i n g

technologies generally use more front-

end-like processes, they include many

structures not used in most front-end

applications, including TSVs, RDLs,

pillars, micro-bumps, and solder bumps.

These are inherently three dimensional

and all bring inspection and measurement

requirements that are unique to advanced

packaging processes.

Metrology and inspection systems

for advanced packag i ng proce sse s

h ave o f t e n a d a p t e d t e c h n o l og i e s

u s e d i n t r a d i t i o n a l f r o n t - e n d o r

b a c k- e n d a p p l i c a t i o n s , b u t s ome

W