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58

Chip Scale Review May • June • 2019

[ChipScaleReview.com]

Figure 7

illustrates a copper pillar bump

and shows full wafer plots of coplanarity,

diameter, and height measurements.

Cracks

Wi t h t he i n t r odu c t i on of l ow- k

d iele c t r ic s a nd ma t e r i a l p r op e r t y

mismatches, the edges of a die are prone

to chipping and cracking during the saw

process. Cracks then propagate into the

active area of the die causing immediate

impact to yield or device reliability

issues downstream, as discussed below:

• Hairline cracks or f ine su r face

cracks generally r un across the

su r face of t he act ive a rea of a

d ie. The i r sma l l si z e a nd low

cont rast make them diff icult to

detect. Existing detection methods

also generate unacceptably large

numbers of false defects, sometimes

as many as 20X the number of real

defects. Die crack detection (DCD)

software uses sophisticated post-

image processing techniques to

enhance the detectability of hairline

cracks by increasing their apparent

size and contrast (

Figure 8

). In

a n expe r iment , DCD sof t wa r e

d e t e c t e d a l l c r a c k s f o u n d by

conventional techniques in addition

to a number of crack defects that

went undetected, while showing

a signif icant reduction in false

positive nuisance defects.

• Sidewall cracks are seen post saw

and protrude past the die seal ring

into the active area of the die. They

are difficult to see because they are

typically below the surface and are

obscured by device patterning. By

combining DCD with die seal ring

(DSR) inspection, these defects

can be detected and classified. In

addit ion, i nf ra red imagi ng can

provide valuable cor roborati ng

evidence that the “disappearing”

sidewall cracks are real and not

nuisance defects (

Figure 9

).

Summary

Many new products are replacing

wire bonding for high-performance

memory technologies that require fast

communication with other chips and

external connections to transport and

store large volumes of data. Flip-chip

and advanced packagi ng processes

provide shorter, denser, more numerous

signal pathways and smaller package

sizes. The t ransition is expected to

continue and accelerate. Although these

packaging technologies use many front-

end-like processes, the unique structures

they create present new challenges for

inspection and metrology. Many of these

challenges are best addressed by sensors

and systems specifically developed for

the application. Rudolph has developed a

flexible suite of inspection and metrology

sensors to address these challenges.

References

1. V L S I R e s e a r c h - p r i v a t e

communication, Feb. 2018.

Figure 7:

(left to right) Copper pillar bump; and full wafer measurements of the bump: coplanarity, diameter

and height.

Figure 8:

(left) Original image of a hairline crack; and (right) DCD enhanced image of the hairline crack.

Biography

Damon Tsai received his Master of Science degree in Laser and

Optical Engineering from National Tsing Hua U. and is Director

of Inspection Product Management at Rudolph Technologies;

email

damon.tsai@rudolphtech.com

Figure 9:

(left) a) 1X bright-field image of sidewall crack, b) (middle) 20X bright-field image of sidewall crack;

and c) (right) 10X IR image of sidewall crack.