Chip Scale Review - May June 2020

26 Chip Scale Review May • June • 2020 [] Embedded trace and 2-in-1 RDL for fan-out panel-level packaging By Kesheng Feng, Kwangsuk Kim, Saminda Dharmarathna, William Bowerman, Jim Watkowski, Johnny Lee, Jordan Kologe [MacDermid Alpha Electronics Solutions] ith respect to fan-out panel-level packaging (FOPLP), fabr icators have struggled to justify the upfront costs of installing the process because of cha l lenge s wit h coppe r plat i ng performance and package cost reduction compared to fan-out wafer-level packaging (FOWLP). A key challenge is obtaining a combination of high line resolution and height uniformity from the copper plating process that forms the circuitry of the redistribution layer (RDL). This is especially challenging in simultaneous plating of traces and filling of vias, in what is called 2-in-1 (RDL) plating. Coplanarity between the surface of the plated copper traces, pads and/or filled vias is a critically important qualifying feature for these copper plating processes. A surface that is not coplanar could result in signal transmission loss and distortion of the circuitry layers after lamination. These defects can cause short circuiting and catastrophic failure of the device. Because of the scale of the circuitry involved, planarization processes that can restore coplanarity can impart registration errors into the layer. Therefore, copper plating solutions providing a uniform surface prof ile without requiring additional post treatment are key to successful implementation of RDL plating for panel-level packaging. In this article, we present a background on the manufacturing technologies that create copper metallization for FOPLP, discuss the chemical and equipment influences on copper electroplating for this application, and examine the performance of a commercial electrolyte system in both embedded trace and 2-in-1 RDL plating. SAP, mSAP, and ETS technologies The technologies currently utilized for manufacturing the RDL for FOPLP include semi-additive processing (SAP), mod if ied semi-add it ive processi ng (mSAP), and embedded trace plating. SAP has been used for making fine lines on organic substrates for decades. The process begins with electroless copper plating to form an ultra-thin conductive seed layer, followed by photolithography to pattern a photo resist on the surface. Electrolytic copper plating is then used to form metallization structures between the photo resist patterns. This is then followed by removal of photo resist and flash etching away the copper seed layer to complete the patterning. SAP has advanced enough to allow wiring dimensions down to 9μm, but due to the small amount of side etching that occurs to the plated copper traces during the flash etching step, there has been a challenge in reducing linewidth scales further. There are also other challenges as line/space trends approach 9µm/9µm, including adhesion to the organic substrate, process tool accuracy across uneven substrate surfaces on panels that can be in the range of 500mm x 400mm in size, plating thickness uniformity, and the high costs of specialized equipment, such as advanced photolithography tools. mSAP is a newer process that has been widely adapted in reducing circuitry dimensions for mobile electronics by effectively fulfilling the utility of printed circuit board (PCB) and integrated circuit (IC) substrate in the device. The typical mSAP f low begins with an organic substrate clad with a very thin copper foil of approximately 1-5µm in thickness. Microvias are then laser drilled and the panels desmeared, either through a plasma or chemical desmear or a combination of both. This process cleans any resin residues from the target pad and imparts topography to the via walls for adhesion of subsequent copper deposits. The panels are then processed through a primary metallization process such as, electroless copper, carbon-based direct metallization, or conductive polymer, to make the via walls conductive for electrolytic copper plating. The panels are subsequently imaged and pattern-plated with electrolytic copper to both fill the microvias completely with copper, and build the copper traces to the required height in a single step. After plating, the resist is stripped and a differential or flash etch is done to form the final circuitry. The fine-line resolution from this technology is typically limited to 13µm dimensions. Embedded trace substrate (ETS) plating technology provides additional cost reduction and higher resolution advantages without a f lash etching step, allowing fine-line resolution approaching 5µm. ETS technology uses a photolithographic process to create pattern-plated copper metallization structures onto a conductive W Figure 1: Combining embedded trace substrate technology (steps 1, 2, 3, and 6) and mSAP technology (steps 4, 5, and 6) in a single process flow.