Chip Scale Review - May June 2020

38 Chip Scale Review May • June • 2020 [ChipScaleReview.com] Demand for 3D devices drives inspection and metrology innovation CSR asked Raj Jammy, President of the Process Control Solutions Business Unit at Carl Zeiss SMT group and President of Carl Zeiss SMT Inc., the North America subsidiary of Carl Zeiss SMT GmbH, to provide an update on how demand for 3D devices is driving inspection and metrology innovation. CSR: 3D devices drive a good deal of semiconductor technologies today and in turn, such devices need to have 3D i nteg r ated i n format ion when it comes to 3D inspection and metrology. Why is imaging alone not sufficient for these devices? RJ: In the pursuit of root cause of failures and process defects, structural information tells only part of the story. Some t h i ng may look s t r uc t u r a l l y sound, but be electrically or chemically defe c t ive. For example: of t en one wants to do energy dispersive X-ray spectroscopy (EDS) analysis of a focused ion beam (FIB) cross section before final transmission electron microscopy (TEM) prep and electron energy loss spectroscopy (EELS) analysis. It can be impor t ant t o unde r st and if any oxidation present at a defect site occurred before exposure to atmosphere, or is a side effect from exposure during the transfer from FIB to TEM. 3D device architectures, indeed, pose significant challenges for all three types of analyses, because of shrinking features that are buried beneath the surface and often not accessible for testing. CSR: Wit h re spect t o sh r i n k i ng features and imaging, how is cross-section accuracy impacted? RJ: Traditional package cross-section approaches have an accuracy in the range of about 15 microns, and it can take two days or longer to prepare a high-quality advanced-package cross section at exactly the right location with minimal artifact. As package interconnects continue to shrink, the ability to cross section to exactly the right location becomes less successful. We are dealing with technologies today in packaging that require nanometer resolution for micron-sized objects located within millimeters of volume. Just as shrinking semiconductor dimensions in the 1990s drove the transition from scanning electron microscopy (SEM) imaging to FIB prep and TEM imaging, today we see the cycle repeat with package fine pitches driving a transition from traditional cross-sectional methods to new cross-section approaches with the speed and accuracy for package interconnects at 50 micron and finer pitches. CSR: What other considerations come into play with respect to cross-sectional methods for advanced packages? RJ: Generally, advanced packages are used for the advanced Si nodes that use fragile dielectric materials in the back end of line (BEOL) Si interconnects. To achieve fine pitches, Cu-pillar solder bumps are being adopted for advanced package interconnects. Cu is a hard material, and the combination of low-modulus brittle materials and hard materials can lead to cracks and delaminations, whether from handling steps of sample preparation or from reliability failures caused by chip- Figure 1: Crossbeam Laser FIB-SEM throughput for each step of the workflow for a customer’s application. Figure 2: Crossbeam Laser FIB-SEM provides fast, high-quality cross sections of Cu-pillar microbumps buried 760µm deep with total time to results of <1 hour.

RkJQdWJsaXNoZXIy ODIzODM4