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Chip Scale Review November • December • 2016


die (see “minor straightness deviation”


Table 1


Figure 7

). In an even rarer

occurrence, the cleave touched the

active die area (see “major straightness

deviation” in

Table 1

). A potential

source of this is an overlaying internal

stress pattern.

In this case study, the wafer had a

massive metal and polyimide ring in

the edge exclusion area on the top side

of the wafer, which was built into the

design rules by the manufacturer. The

influence of this ring was visible and

caused damage to a few die behind

t h e e d g e e x c l u s i o n ( s e e “ c l e a v e

failure by outer metal ring” in



). This error pattern can easily be

a vo i d e d by imp l eme n t i ng a l a s e r

clearing step comparable to the metal

pattern opening in the dicing streets.

Alternatively, this clearing step can be

avoided by modifying the design rules

to exclude any outer metal rings.

As an outcome of this case study, it is

suggested to either avoid designing in

the metal ring, or take a less restrictive

a p p r o a c h a n d r emo v e t h e me t a l

ring by implementing an additional

laser clearing step. In both cases,

the expected yield will increase an

additional 0.8% (to a total yield count

of 99.74%). Dies from a comparable

wafer have been packaged, and after

thermo-cycling only one out of 106

dies failed the leakage current test. The

cause of this defect is believed to be

unrelated to the new process.

Additional implications

In addition to yield improvement,

the new process has demonstrated a

significant improvement in terms of

cost per wafer. A typical mechanical

sawing process wears one saw blade

per wafer due to the enormous hardness

of SiC. As noted earlier, this problem is

compounded on larger diameter wafers,

and is likely to result in requiring an

additional blade to completely cut a

6-inch wafer. To match the throughput

of the TLS process, an investment in

nine times more mechanical sawing

t oo l s i s r equ i r ed . Tak i ng t h i s and

additional factors into consideration

such as cost of consumables, projected

tool depreciation and footprint (one

microDICE system using TLS-Dicing

technology versus nine blade saws),

the overall cost per wafer is projected

to reach up to $41.69 per 6-inch wafer

for mechanical sawing, but only $2.70

per 6-inch wafer for the microDICE/

TLS system. This does not factor in

additional cost considerations such

a s r educed t oo l ope r a t o r cos t s by

using a single

m i c r o D I C E

s y s t e m

compared to the

s i g n i f i c a n t l y

greater number

o f mechan i ca l

b l a d e d i c i n g

t oo l s , no r t h e

increased yield

enabled by the

n e w d i c i n g



Thermal laser separation is a new

approach to separating brittle materials

at high throughput, low cost, and with

high separation quality. The cleaving

principle shows unique advantages

for SiC-based products with backside

metallization, such as power devices.

The case study highlighted in this

white paper demonstrated a very high

separation yield of 98.9%. This is

an average value for a small batch

of 4-inch SiC product wafers with

backside metal, metal structures in the

street on the front side, and polyimide

on the dies.

The new process has demonstrated

un i qu e a dv a n t a g e s f o r S i C- b a s e d

power devices. Investigations and

developments for other applications

and materials (including silicon) are in

preparation. For example, the ability to

cleave without any particle generation

could be an interesting option for flip-

ch i p app l i ca t i ons , such a s MEMS

and 3D-packaged wafers with solder

bumps. At the same time, the ability

to provide zero kerf cleaving could

have a noticeable impact on die yields

where smaller die sizes are involved

and reduced street widths could enable

more die per wafer.


1. K. O. Dohnke, et al., “Comparison

of different novel chip separation

methods for 4H-SiC,” Materials

Science Forum, Vols 821-823 (2015)

pp. 520-523.


TLS-Di c i ng and mi c r oDICE a r e

trademarks of 3D-Micromac AG.

This research was partially supported by

Fraunhofer IISB, Germany.


Hans-Ulrich Zuehlke holds a PhD

in Natural Sciences from the Friedrich

Schiller U. Jena, Germany, and is Market

Development Manager at 3D-Micromac

AG; emai


Mandy Gebhardt received an MBA in

Economic Computer Science from the U.

of Cooperative Education Glauchau and is

Marketing Manager at 3D-Micromac AG.

Figure 6:

This photo shows the perpendicular cleave

exit at the wafer’s edge, which is not yield-relevant

due to residing in the in-edge exclusion zone.

Figure 7:

Example of minor deviation with no

influence on the electrical function.

Table 1:

Resulting average yield and yield losses by categories.