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Chip Scale Review November • December • 2016

[ChipScaleReview.com]

of the conference was “Bridging the

Interconnect Gap,” thus highlighting one

of the major challenges our industry is

facing as “big data” seeps into our daily

lives in multiple forms at the workplace,

home, and in between.

he 13th International Wafer-

Level Packaging Conference

(IWLPC) and Exhibition,

held in Silicon Valley on

October 18-20, offered an excellent

insight into current issues and future

challenges in advanced packaging

technologies. An impressive array

of 48 presentations, five interactive

presentations (poster sessions), and

four workshops covered a wide array of

topics with focus on various aspects of

fan-out wafer-level packaging (FOWLP),

3D packaging and manufacturing,

and microelectromechanical systems

(MEMS). Overall, attendance was higher

than what I’ve seen in past years, and

the expo hall was sold out completely.

Table-top exhibitors, who couldn’t get

space inside the main exhibition hall,

lined up their display items along the

walkways in front of the main exhibit

area. Quite fittingly, the main theme

Reflections on IWLPC 2016

By Louis Burgyan

[LTEC Corporation]

Co g n i t i v e c omp u t i n g , mo b i l e

communication, connected vehicles,

cloud-connected Internet of Things

( I oT ) d e v i c e s—a l l r e q u i r e f a s t

processing locally and through the

cloud with access to massive amounts

of data, regardless of its location. The

brick and mortar of the underlying

hardware environment is advanced

packaging technology that needs to

facilitate interconnectivity among

often heterogeneous systems within a

package. Processors, memories, and

logic devices need to interact at multi-

gigabit per second data rates. Those

vastly improved latencies attained

by 3D NAND flash memory stacks

must not get compromised by data

paths within various building blocks

assembled in 2.5D or 3D systems in a

package. Similarly, data and information

gene r a t ed by sensor s need t o be

processed, interpreted, and transmitted

through communication systems with

high signal and power integrity.

The focus of this event was wafer-

level packaging (WLP) and FOWLP

t e c hno l ogy. Wi t h t h e e vo l u t i on

of semi conduc t or manuf ac t ur i ng

processes, minimum feature size

decreases and functionality built into

the die increases along with I/O count,

and heat generation within the die

often increases. FOWLP technology

offers a practical and cost-effective

solution by creating additional surface

area around the semiconductor die

where I/O terminals can be placed.

Ou twa rd rou t i ng f rom t he d i e i s

facilitated by adding a redistribution

layer (RDL) structure having one or

more routing layers.

Implementation of the systems noted

above, often in application-driven form

factors, presents formidable challenges

to outsourced semiconductor and test

suppliers (OSATS) and circuit and

T

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