Previous Page  46 / 52 Next Page
Show Menu
Previous Page 46 / 52 Next Page
Page Background


Chip Scale Review November • December • 2016


systems designers alike. Circuit and

system performance can no longer

be separated from the packaging

technology deployed. As noted by

several presenters at the conference,

the new paradigm is a collaborative

approach between circuit/system

and package design teams. One of

the speakers at a panel discussion

cited an example of the exemplary

collaboration between Apple’s design

teams and TSMC’s developers of

the highly advanced Integrated Fan-

Out Wafer-Level Packaging (InFO-

WLP) technology deployed in the A10

processor of the iPhone7.

Given this backdrop, in his keynote

address, Prof. Rao R. Tummala of

Geo rg i a I ns t i t u t e o f Techno l ogy

discussed the future of fan-out wafer-

level technologies and active/passive

component embedding. In another

keynote presentation, Prof. Klaus-

Dieter Lang, Director of Fraunhofer

IZM, outlined his vision of advanced

manufacturing technology platforms

required to serve the needs of a diverse

field of cyber-physical systems. Dr.

Lang highlighted an existing gap

between wafer-panel and rectangular

PCB-panel infrastructures in the 2-20μm

L/S range and stressed the need to find

reliable, low-cost solutions.

Panel discussions

Large-area rectangular panel


Participants of a panel

discussion, moderated by Jan Vardaman

of TechSearch International, examined

the potential cost savings and existing

barriers that large-area rectangular

panel processing needs to overcome

before 2.5D and 3D FOWLP system-

in-package (SiP) structures having less

than 20μm L/S could be fabricated

i n a h i gh-vo l ume manuf ac t ur i ng

environment. Per estimates, most cost

benefits stemming from increased

throughput can be attained at a roughly

600mm x 600mm panel size. The larger

the individual package size, the larger

the saving. For example, at a 10mm

x 10mm package size, a 25-30% cost

reduction is realizable; however, at a

4mm x 4mm or smaller package size,

there is no cost saving.

The need for optical systems having

higher accuracy and depth of focus to

accommodate processing of large warped

wafers with high yield and reliability

was discussed. The lack of standards and

requirement for die-shift error correction

were also highlighted. Panel processing

plant tooling costs were estimated to be

over $150 million. Panelists suggested

that IoT and the requirement for

processing massive amounts of data in

the coming years ahead are likely to be

the market driver that finally ushers fine-

pitch fan-out panel-level packaging (FO-

PLP) into mass production.

Chip-package interaction.

Dr. Urmi

Ray of Qualcomm moderated another

panel discussion on chip-package

interaction (CPI) and its impact on

products fabricated for the commercial,

automotive, and defense sectors.

The discussion followed two paths:

mechanical CPI (mCPI) and electrical

23–25 JAN2017 GRENOBLE,  FRANCE A cutting-edge con- ference and exhibition that brings together the entire 3D supply chain and focuses on the technologies that enable higher density products. Attend to Connect! CREATING HIGH DENSITY SYSTEMS Conference Exhibition Networking