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Chip Scale Review November • December • 2016

[] TheWorld’s Premier evenT forWhaT’s Now & Next inTesT & Burn-in of Packaged ic’s The annual BiTs Workshop—now celebrating its eighteenth year—brings together experts and exhibitors in the field of test and burn-in from around the world. Join your colleagues in arizona for four days of speakers, technical programs, networking opportunities, BiTs eXPo, and more! W W W . B i T s W o r k s h o P . o r g Publication SPonSor Premier SPonSor Register now! m a r c h 5 — 8 , 2 0 1 7 • m e s a , a r i z o n a

CPI (eCPI). Many attendees asked

specific questions concerning back-end-

of-line (BEOL) separation, metal line

breakage, warpage, die thinning, issues

related to thick Cu RDL, advanced

p r oce s s node s us i ng u l t r a l ow- k

materials, and new failure mechanisms.

The long list of concerns underscored

the need for consistent process control,

predictive modeling, and tracking and

understanding failure mechanisms.

Session highlights

Concerning session highlights, it is

impossible to offer a comprehensive

o v e r v i ew o f s o ma n y e x c e l l e n t

presentations in a short article, however

a few are highlighted below.

Dr. Habib Hichri

of SUSS MicroTec

described a full-field scanning exposure

system with a 1:1 projection lens

suitable for high-resolution patterning

and large depth of focus. These features

and the 30x30mm field size are essential

for working with thick photoresist

and warped 300mm wafers or large

rectangular panels. The system has

closed-loop projection mask temperature

control to facilitate use of low-cost soda

lime masks. The system has software to

correct for die placement errors, and it

is capable of supporting <3µm L/S at

50% lower cost-of-ownership relative to

UV steppers.