Previous Page  44 / 52 Next Page
Information
Show Menu
Previous Page 44 / 52 Next Page
Page Background

42

Chip Scale Review November • December • 2017

[ChipScaleReview.com]

Optimization of speed and accuracy for fan-out

die placement

By Tom Strothmann

[Kulicke & Soffa]

an-out processes represent the

fastest growing segment of

electronics packaging market

with a projected compound annual growth

rate (CAGR) of nearly 50% for the period

of 2016 through 2020. The rapid increase

in volume has primarily been driven by

the mobile space where fan-out packages

offer the most compact form factor and low

cost. One of the key enabling technologies

for fan out is the die placement process,

however die placement requirements for

fan-out wafer-level packaging vary widely

based on the process flow selected. Fan-out

process flows can require die placement

to be done face up or face down and

alignment schemes for die placement can

include global alignment, local alignment,

or a combination of both methods. In some

flows, heat may be required for the carrier

or the die and placement force must be

carefully controlled. Each process flow has

attributes that define the challenges and

requirements for die placement conditions,

but machines with heat, force and local

align capability have higher cost and

lower units per hour (UPH). These factors

contribute to a higher depreciated cost

applied to each unit produced, as well as

a higher initial capital cost, and must be

considered when selecting the best fan-out

flow for a given product.

Accuracy requirements are driven by

the photolithography steps done after

reconstitution and steppers are commonly

used with the assumption that die-to-

die spacing is repeatable within a given

field area. Die spacing will inevitably be

somewhat irregular on account of normal

process variation in the placement and

reconstitution processes, although variability

can be reduced with the proper selection of

placement equipment and molding materials.

Die placement accuracy in conjunction

with die shift during the reconstitution

process must accommodate the design rules

for redistribution layer (RDL) via size,

passivation opening size, and pad pitch for

the intended devices. The selection of die

placement equipment is important because

equipment optimized for the best accuracy

may not have the highest UPH. This trade-

off between speed and accuracy should

be considered in the selection of the fan-

out process to ensure the final product can

be produced with the most competitive

cost. It is important for manufacturers to

understand the interaction of these factors in

the selection and optimization of their fan-

out process flows because the choice of the

process flow imposes constraints that affect

the final cost of the die placement process.

FOWLP standard process flows

Three basic process flows have emerged

in the industry. The diagram in

Figure 1

graphically represents the options in high-

volume manufacturing (HVM) today and

some of the die placement requirements for

each. Although the TSMC integrated fan-out

(InFO) flow has garnered the most attention

recently, the embedded wafer-level ball

grid array (eWLB) process

flow licensed by Infineon

has by far the highest

volume in production

today. The eWLB process

flow is currently offered

by STATS ChipPAC, ASE,

and NANIUM S.A. (now

Amkor Technology). The

products using the eWLB

process flow are typically

single-die products with

low I/O counts such as

PMICS, audio codecs, and

RF. These “low density”

products represent about

75% of the total fan-out

wafer-level packaging

(FOWLP) volume and that

percentage is expected to

remain relatively stable as

volumes increase through

2020. The three standard

fan-out process flows

supporting these options are

shown in

Figure 2

.

D i e p l acemen t ac cu r ac y and

alignment schemes

The two alignment methods used for

die placement in fan-out processes are

global alignment and local alignment.

For global alignment, all die are aligned

to a common Cartesian reference frame

determined by two or more global

fiducials placed on the edge of the carrier.

Global alignment provides the fastest die

placement and therefore the lowest cost.

This method typically requires careful

mapping of machine axes to ensure

accuracy is maintained over the full

work area. Accuracy achieved with this

method is typically limited to 5µm for

the highest speeds. Global alignment is

predominantly used in the eWLB process

flow with face-down chip-first placement,

but it can be used in other flows as well.

Global alignment is depicted in

Figure 3

where a carrier is shown with placed die

and global fiducials.

F

Figure 1:

HVM FOWLP process options.

Figure 2:

Standard process flows for FOWLP.