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Chip Scale Review November • December • 2018


Heterogeneous integration by collective

die-to-wafer bonding

By Thomas Uhrmann, Jürgen Burggraf, Mariana Pires, Martin Eibelhuber

[EV Group]

ncreasing integration of technology,

sensing and real-time data analysis

using artificial intelligence are

at the same time changing chip design

and integration. Where a continuous

evolution in feature scaling has historically

been the right approach to chip designs

for information and data storage centric

environments, the current emphasis on

connectivity, big data analysis, artificial

intelligence, augmented realit y and

autonomous vehicles favors different chip

designs, materials and technologies that

are not fully compatible [1]. In addition,

the multitude of new applications enabled

by these industry drivers, along with the

need for faster development cycle times

and high-volume scaling, are introducing

further challenges to overcome. In recent

years, the semiconductor industry has

been experiencing a new revolution of

heterogeneous integration, whereby

interconnection and advanced packaging

technologies are supplanting lithographic

scaling as the main cont r ibutors to

improved device performance [2].

Heterogeneous integration describes

the coalescence of multiple developments

of the past decade. For example, 3D

integration technologies have emerged

and are widely available in high-volume

manufacturing environments. In addition,

several advanced packaging technologies,

such as fan-out wafer-level packaging

(FOWLP) and interposers, are also moving

to high-volume production. Depending

on the device architecture and level of

integration, several integration methods at

different manufacturing levels will play a

major role in heterogeneous integration.

In particular, increasing requirements

for minimum latency and low-power

consumption will drive the industry to new

chip design concepts where integration

of multiple functions such as sensing,

photonics, RF communication, and even

power devices on a single chip will be

crucial. In other words, the chip design

and functional integration will be key.

Silicon processing will certainly play

a key role in enabling heterogeneous

integration. However, silicon by itself

does not provide all of the necessary

f u n c t i o n a l i t y o f h e t e r o g e n e o u s

integration. Therefore, material transfer

and functional die transfer technologies

involving different materials will be

increasingly important to simultaneously

enable silicon processing and close

integration of the compute, sensing and

connectivity portions of a fully functional

system on chip (SoC).

Wafer bonding—especially fusion and

hybrid wafer bonding—is readily available

in mass production at major foundries and

integrated device manufacturers, and is

beginning to be adopted among system

integration-oriented packaging houses.

While the current driving forces for wafer-

to-wafer (W2W) fusion bonding are 3D

integration processes for stacked memory

and image sensors, W2W bonding requires

matching die sizes.

I n o r d e r t o e f f i c i e n t l y b u i l d

heterogeneous systems, several dies with

different sizes have to be joined, which

means integration on the chip level. This

in turn means that different silicon nodes,

compound semiconductors for photonic

and power devices or RF filters coming

from different fabs on different wafer sizes

all need to find their way onto the same

silicon base substrate. While fusion and

hybrid bonding are compatible with front-

end manufacturing, sequential die-to-

wafer (D2W) approaches are not. In many

cases, D2W processing involves several

hours of placement time, which exposes

the process to particle generation. This

makes it difficult to integrate with particle

sensitive processes such as fusion bonding.

While particle requirements as stringent

as ISO 1 can in principle be mastered

inside the equipment, the D2W population

time and the act of moving the bond

heads over the wafer will influence yields

considerably. Therefore, D2W equipment

will be detrimental for heterogeneous

integration. How, therefore, does one

surmount this dilemma?

Collective die-to-wafer bonding

The only logical solution is a collective

bonding approach. In this way, process

s e p a r a t i o n o f d i e p l a c eme n t a n d

fusion bonding enables high bonding

yields while keeping D2W equipment

complexity at a manageable level. The

process flow of collective D2W bonding

is depicted in

Figure 1

. The initial step is

the preparation and surface conservation

of the source wafer prior to dicing.

Because dicing processes are prone to

heavy particle generation on the wafer

surface and can even generate surface

defects on the nanometer scale, the fusion

bond interface needs to be conserved

by a protective f ilm. In addition to

being smooth and having homogeneous

thickness, the protective film has to

be cleanable and not leave behind any

organic residues.

I n a subsequent step, each die is

placed on a car r ier subst rate using

D2W equipment. Depending on the


Figure 1:

Schematic process flow for the collective die-to-wafer bonding process.