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Chip Scale Review November • December • 2018


Chip-first or chip-last?

For chip-first processes, singulated dies

are placed onto a substrate processed with

temporary bonding material or thermal

release tape (TRT) prior to being over-

molded with epoxy mold compound (EMC)

in a thermocompression process. High-

temperature dielectric processing induces

stress and leads to warpage between the

carrier wafer and EMC. Die-shift and die

stand-off due to substrate warpage and

bonding material softening during EMC

processing creates RDL misalignment to the

embedded die [3].

In a chip-last process f low, glass

c a r r i e r wa f e r s a r e c o a t e d w i t h a

removable laser release material upon

which the RDL will be built. The laser

release material needs to possess good

t he rmal, mechan ical and chemical

stability to survive thinning and backside

dielectric and deposition processes.

Materials for FOWLP



T1100 thermoplastic

bonding materials and BrewerBOND


C130 0 c u r abl e bond i ng ma t e r i a l s

r e p r e s e n t t h e n e x t - g e n e r a t i o n

bond i ng system to of fe r i nc rea sed

throughput with high thermal stability.

T h e s e ma t e r i a l s o f f e r i mp r ov e d

me c h a n i c a l s t a b i l i t y a t e l e v a t e d

process temperatures, good chemical

resistance, room temperature bonding

and debonding for both wafer-level

and panel-level processing. The low

total thickness variation (TTV) coupled

with the increased mechanical strength

of t h is system allows for ult rat h i n

backside wafer thinning, achieving

p o s t - g r i n d wa f e r t h i c k n e s s e s o f


F i gure 1

shows con fo c a l

scann i ng acoust ic images (CSAM)

of a bonded wafer pair after thinning

t o 5 0 µ m a n d s u b s e q u e n t h e a t

t reatment at 400°C for 30 mi nutes

under vacuum. These images show a

defect-free bondline without damage to

the thin device.

High-temperature survivability and the processes

it enables

By Michelle Fowler, Christopher Apanius, Kimberly Yess

[Brewer Science, Inc.]

ith all the improvements

i n t h e a d v a n c e d

packaging landscape,

what more could the industry ask for? After

addressing performance expectations:

total thickness variation (TTV), stress/

warpage control, high throughput and low

cost of ownership, what could possibly be

left? Extreme temperature survivability,

perhaps? Industry applications today are

requiring devices to be thinned down well

below 30µm, which ultimately will require

a carrier system for handling fragile, high-

value substrates through the subsequent

downstream processes including high-

temperature anneal and deposition. The

challenges that occur at the packaging level

are well understood. We have developed

technologies to overcome these challenges

at the wafer level before the thinned device

chips ever make it to packaging—further

adding value and performance while

reducing cost of ownership. The objective of

this article is to explain and show examples

of new high-temperature-compatible

materials and in-process solutions during

fabrication of the device. These new

materials have demonstrated improved

performance beyond any other solutions

known today. Applications that benefit

from using higher-value chips fabricated

using this enabling new technology will be

explored along with examples.

Wafer-level challenges

Wa f e r- l e v e l p a c k a g i n g ( WL P)

technologies have been widely adopted

for large-scale production and used for the

manufacturing of consumer products such

as smartphones, tablets and various other

hand-held devices. Higher-performance

packaging, lower cost, smaller form factor

and a higher level of integration can be

achieved using various packaging platforms.

Wafer-level chip-scale packaging (WLCSP)

is attractive due to its cost and performance

ratio and substrate-less package, however,

its use is limited by die size. As an

alternative, fan-out wafer-level packaging

(FOWLP) technology is being widely

developed and used in the packaging in-

dustry because I/O density can be increased

by “fanning” out interconnects to external

pad locations, achieving smaller form

factor and decreasing power consumption.

Semiconductor packaging technologies with

heterogeneous integration, such as system-

in-package (SiP) and package-on-package

(PoP) infrastructures are facing significant

challenges due to increased complex

integration. The demands for improved

system performance, functionality, lower

power and smaller form factor are the

drivers of today’s packaging technologies.

Substrate handling of the thinned device

is a major challenge for the manufacturing

f low for many of these technologies.

Th i n ned si l icon wa fe r s <50µm o r

redistribution layers (RDLs) created using an

RDL-first process are delicate and expensive

to manufacture. Handling requires the

use of support substrates processed using

temporary bonding materials along with an

applicable debonding (TBDB) technology

to facilitate the construction of complex

packaging infrastructures [1].

Temporary bonding materials created

using high-viscosity, low-T



polymers are commonly used in TBDB

processes. When used with a carrier

substrate, they offer thermomechanical

stability and improved ease of handling

of the thin device substrate. At higher

temperatures these materials behave more

like a liquid and lose mechanical stability

as the melt viscosity decreases allowing

the material to soften, thereby weakening

bondline stability. Deformation and

delamination of the device wafer can occur,

causing issues for downstream processes [2].

Both chip-first and chip-last process

flows require the use of high-temperature

and high-vacuum processes to create the

RDLs. Today’s FOWLP processes require

materials that can survive high temperatures

and harsh chemical environments while

maintaining mechanical support for the

device substrate.