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Chip Scale Review November • December • 2018

[ChipScaleReview.com]

complexity increase factor by multiplying

some of the major parameters, such as

package size, silicon size, thermal, and

power challenge.

Table 1

shows the

magnitude of these combined changes.

Th is sh if t t owa rd more complex

integration is further illustrated through

industry participation in conferences: the

growth of the leading packaging conference

(ECTC) has more than doubled in the last

decade. The five leading sessions this year

focused on complex fan-out, or wafer-

level packaging – with more than twice

the attendance of the flip-chip or materials

sessions that have historically dominated

the conference.

A momentous change is happening

with visibly significant shifts reaching the

(traditionally conservative) networking

market, as 2.5D and remarkably complex

multi-chip module (MCM) configurations

Integration madness

By Wolfgang Sauter, Mark Kuemerle

[Avera Semi, a wholly owned subsidiary of GLOBALFOUNDRIES]

hile package integration

has revolutionized the

handheld applicat ion

space, the infrastructure market has

remained comparatively conventional.

Yet change begins now! Sparked largely

by the complex packaging required by

high-bandwidth memory (HBM), new

architectures have emerged utilizing

appreciably advanced integrated solutions.

In this article we will investigate the factors

driving this new direction, and what types of

chip-to-chip I/O will be required.

Package integration has recently driven

stunning innovation in the handheld

application space. The complex fan-out

packages being used for today’s cell phone

processors are extremely small, and feature

an integrated package height that is thinner

than the substrate alone was a few years ago.

In addition to the processor chip, memory

components and sophisticated power supply

networks are now being integrated in these

increasingly complex packages.

Packaging innovations also drive changes

in chip architectures: the design blocks on

a chip that enable communication between

different chips (“interface intellectual

property [IP]”) are evolving to allow the

short connections in a low-power, and

bandwidth-efficient way. Interface IP blocks

must now be designed to match, and take

advantage of specific package technology

integration schemes.

So what does this mean? Is packaging to

rule the next wave of innovation? This remains

to be seen. At the highest level, we can separate

themarket into two application spaces:

1. The high-volume, space-constraint

consumer market with fairly low

reliability requirements. (Do you own a

cell phone that is more than 3 years old?)

2. The low-volume, high-reliability

infrastructure market (networking,

etc.), requiring large package sizes, yet

need to survive in the field for 10 or

more years.

As consumer applications have evolved

through greater package integration in

the last decade, networking and compute

applications remained in much more

conservative package solutions, primarily

(if not exclusively) single-chip modules.

There have cer t ainly been package

technology changes and innovations

driven by HSS (SERDES) speed and

performance requirements, but suffice it to

say, the majority of these changes have been

evolutionary: larger chips (up to reticle size),

larger packages (up to 75mm), and newer

materials with lower loss dielectrics.

The slow, steady growth described above

has been supported by ever-increasing

SERDES data rates and novel serial

memory solutions like the hybrid memory

cube (HMC). Yet recently there has been

a marked shift in package complexity for

these applications driven largely by HBM

integration, a massive shift in system

complexity and risk beyond previous

applications. It seems that

HBM’s requirements have

broken through system-level

constraints in a way that

this market has never before

seen. Larger-than reticle size

inter poser solutions with

HBM integration as shown in

Figure 1

serve as examples of

products entering the market

this year.

W h i l e t h e r e a r e n o

object ive mea su re s t hat

can be used to quant if y

the increase in complexity

of these new applications,

we can calculate a rough

W

Table 1:

Increased package complexity of solutions within the last product generation.

Figure 1:

Example of 2.5D integration on a stitched silicon interposer.