Previous Page  27 / 52 Next Page
Information
Show Menu
Previous Page 27 / 52 Next Page
Page Background

25

Chip Scale Review November • December • 2018

[ChipScaleReview.com]

The best example of a parallel interface is

the HBM: over 1,000 signal wires running

at 2Gbps enable 2Tbps of bandwidth, but

drive the need for a silicon interposer to

enable the signal count.

Other approaches for interface options

are somewhat in-between a traditional

SERDES and a parallel interface (we

can call them “weird serial” for now).

These approaches include fast I/O with

equalization built into the signaling

scheme, single-ended serial interfaces,

etc. There are currently at least five

similar but competing nonst andard

i nter faces proposed f rom dif ferent

original equipment manufacturers (OEMs)

and IP providers. Unfortunately, none of

these are really interoperable with each

other.

Aiming to influence the direction of

interface standardization, alliances (e.g.,

USR Alliance) have formed, proposing

different approaches while st r iving

to emerge with the industry-standard

solution. All options have pros and cons,

and none have yet found widespread

adoption, but they all share the need to be

custom-tailored with specific packaging

technologies.

Looking forward, all of the package

integration plays described so far are

based on 2-dimensional side-by-side

integration of chips (even if we call them

2.1D, 2.3D, or 2.5D). While the trace

lengths of a couple of millimeters between

chips sounds short, there is significant

opportunity to further reduce I/O power

when considering true 3D integration.

Current expectations suggest a 90-95%

reduction in interface power for 3D

integration compared to 2-dimensional

integration. This is due to:

• Lower load capacitance of the ~50µm

long TSV compared to an ~2mm long

signal trace;

• Lower I/O drive strength; and

• Elimination of any need for equalization

or termination.

In addition to this tremendous power

reduction, the small size and density of the

TSVs enable higher signal density between

chips, and therefore also orders of magnitude

greater bandwidth.

Summary

The approach of creating discrete

modules for specific purposes is ending

and will be replaced by more complex

packaging integration. The best solution will

be the one offering the greatest bandwidth

and the lowest power per transferred bit.

While we will inevitably encounter even

more outlandish proposals along the way,

the ultimate solution will be 3D integration.

Biographies

Wolfgang Sauter received his MS in

Mechanical Engineering at The Technical

U. of Munich and his PhD in Mechanical

Engineering at the U. of Vermont. He is

a Distinguished Member of Technical

Staff at Avera Semi, a wholly owned

subsidiary of GLOBALFOUNDRIES;

Wolfgang.Sauter@globalfoundries.com

Mark Kuemerle received his MS from

Case Western Reserve U. He is a Fellow

for Integrated Systems Architecture

at Avera Semi, a wholly owned subsidiary

of GLOBALFOUNDRIES.

Application expertise from R&D to Production 480.893.1630 Schedule a demo with your devices www.finetechusa.com Sub-Micron Die Bonders 0.5 m accuracy Application flexibility Process repeatability Customized solutions 3 Sigma