Previous Page  41 / 52 Next Page
Information
Show Menu
Previous Page 41 / 52 Next Page
Page Background

39

Chip Scale Review November • December • 2018

[ChipScaleReview.com]

Package assembly design kits bring value to

semiconductor designs

By Ruben Fuentes, August Miller, Jonathan Micksch

[Amkor Technology, Inc.]

o d a y ’s s t a t e - o f - t h e - a r t

pa ckag i ng de sig n s a l low

semiconductor companies

and their customers to implement the

latest technologies and deliver the “wow-

factor” with an ever-increasing number of

features and options in space-constrained

form factors. Other system constraints

include: time to market, design cycle

time, accuracy, productivity and more.

To simplify the design of the newest

advanced packages, such as high-density

fan-out (HDFO) and to address all these

other constraints, Amkor has introduced the

SmartPackage™ Package Assembly Design

Kit (PADK). This article will discuss the

need and value of such design kits.

The value of design kits

Semiconductor and integrated circuit (IC)

designers have used process design kits

(PDKs) for decades to achieve design for

manufacturability (DfM). These foundry-

specific PDKs are used with electronic

design automation (EDA) tools in the chip

design process. These checks are known by

IC designers as layout vs. schematic (LVS)

and layout vs. layout (LVL) – terms that are

not used in the packaging world.

For outsourced semiconductor assembly

and test suppliers (OSATS), package designs

have relied on verification methods such as

design rule checks (DRC) in computer-aided

design (CAD) software and other EDA

verification methods such as computer-

aided manufacturing (CAM) checks. The

combination of these checks ensures that

each package design meets the intended

manufacturing and assembly requirements.

Adding packaging to the PDK

methodology

As die and package integration complexity

continues to increase with 2.5D and 3D

structures, so does the need to integrate a

die- and package-level verification process

– basically, it is the integration of the PDK

in IC design and DRC and CAM checks

in advanced packaging. An example

of this advanced package complexity

with redistribution layers (RDLs), vias,

interposers, and more is shown in

Figure 1

.

The newest advanced packaging designs,

such as high-density fan-out, are at the

intersection of the IC design world and the

packaging design world. Because PDKs

have been used in IC design for many years,

they provide an established approach for

advanced packages as well. Taking tools

that were used exclusively for IC design and

applying them to package design creates a

bridge between the two domains.

Gerber data is the de facto standard used for

exchanging data in the printed circuit board

industry and is the typical packaging design

export for artwork generation. In contrast,

the de facto industry standard for IC designs

export is GDSII for data exchange of ICs and

IC layouts. For HDFO packaging, where the

final layers are actually semiconductor-type

processes, the GDSII data is essential and a

natural extension for design data transfer and

provides the best of both worlds.

The existing package design approach

is shown in

Figure 2

. Once the user

selects a specific package, the packaging

supplier provides the design rules. Each

customer has their own design database

setup where they adapt the package

design rules to their specific database

T

Figure 1:

HDFO package-on-package (PoP) structures

showing a) tall copper pillars on both the right- and left-

hand sides; and b) an HDFO cross section.

Figure 2:

The traditional package verification process.