Chip Scale Review - November December 2019

30 Chip Scale Review November • December • 2019 [ChipScaleReview.com] Enabling 3D packaging using excimer lasers By Ralph Delmdahl, Dirk Müller [Coherent] ; Habib Hichri [SUSS MicroTec Photonic Systems Inc.] h e r e l e n t l e s s d e m a n d f o r sma l l e r a n d l i g h t e r product s wit h fa st e r a nd more powerful processing capabilities continues to be the overarching trend a c r o s s ne a r l y eve r y s e c t o r of t he ele c t r on ic s ma r ke t : f r om t ele com systems to medical sensors, image processing, and of course, smart phones and similar devices. Today, advanced package integration (API) is arguably the key technological enabler supporting this t rend, with a focus on ver tical stacking platforms – so-called 2.5D and 3D architectures – or fan-out wafer- level packaging (FOWLP) as preferred in high-bandwidth memory (HBM). A typical example of 2.5D combines separate computing and communications dies in the same package (system-in- package, or SiP) where the heterogeneous chips are massively interconnected using a high-density interposer or embedded multi-die interconnect bridge (EMIB). An example of a true 3D package is where two (or more) thinned chips are stacked on top of each other in the same molded package, such as several memory chips or the combination of a logic chip and a memory chip. In 2.5D/3D packages where two chips are vertically stacked, a structured layer called an interposer is required. In fan-out, the dies are packaged in molding compound while still on a wafer and do not require an interposer, making it more economical than 2.5D/3D for some applications. Of course, there are several variants of each of these advanced package t ypes. For example, there are th ree types of fan-out packages: chip-first/ face - down; ch ip -f i r st /face -up; and chip-last or redistribution layer (RDL) f i r st . But , a common r equ i r ement for all these is dense high-resolution interconnections, often with extremely thin wafers in order to deliver maximum speed and functionality. As wafers get thinner and electrical lines get smaller, 3D packaging inevitably requires a combination of new processing tasks and established processes that are being pushed to new levels of miniaturization. In this article, we take a look at several of these processes that now can be optimally performed using excimer lasers – powerful ultraviolet lasers long- established in smart display fabrication and in front-end lithography. Patterning dual damascene As packaging technology continues to move towards fan-out architectures, packages with multiple chips requiring intricate designs are becoming more a nd mo r e p r e va l e n t . Cu r r e n t a nd projected designs feat u re up to 10 RDLs, line widths as small as 2µm, v i a o p e n i ng s o f l e s s t h a n 10µm , and ideally, these designs could be transferred to panel-level packaging. Th i s level of adva nced pa ckag i ng could be used in several applications such as wafer-level chip-scale packages ( W L C S P ) : 2 0 0 / 3 0 0 m m ( R D L , integrated passive devices), fan-out WLP: >300mm (eQLB, redistributed ch ip packag i ng [RCP], ot her), and embedded IC: >300mm (f lip-chip ball grid array [FCBGA], f lip-chip chip- scale package [FCCSP]). Among the technical challenges of multiple RDL layers, such as small pitch and small vias, one must also consider planarization to stay within the depth of field (DOF) for exposure tools. Add it ional conce r ns a re t he thermal and mechanical stability of dielectric material, efficient removal of Cu overburden and the seed layer without damaging plated metal, as well as the stability of the deposited metal. Tr a d i t i o n a l o r g a n i c f l i p - c h i p substrates are facing many challenges when it comes to advanced packaging. Photosensitive spin-on dielectrics for via formation, in combination with RDL photoresist, are unable to meet the technical challenges without causing serious concerns about pattern integrity and reliabilit y. Free -st andi ng RDL lines with ≤2/2µm L/S size demonstrate major electromigration concerns, and it is almost impossible to remove the seed layer from narrow trenches—and when it can be removed, it causes severe undercut to the RDL lines. The non- planar surface presents an additional challenge for the next redistribution layer because it requires a larger depth of focus for the exposure system, which then limits the resolution capabilities. Another concern is the warpage of the substrate as more and more layers of RDL are added during processing. This requires careful selection of material while also paying close attention to thermal properties. The pulsed ultraviolet excimer laser is a widely used tool in the electronics and display industries. Lower power versions are used in f ront-end chip mic r ol it hog r aphy a nd h ig h - powe r versions are used to anneal silicon for high-resolution displays and to perform lif t-off of f lexible displays. With a 300W excimer laser for RDL patterning, the rectangular light beam is reshaped a nd pa s s e d t h r oug h a n a l um i num photomask that is the inverse of the via or trench pattern. The patterned beam is then projected onto the substrate surface through a reduction lens. In an automated tool like the SUSS ELP300, the pat ter n is sequent ially stepped across the wafer ( Figure 1 ). Wh e r e a s l i t h o g r a p h y i n vo l v e s photog r aph ic exposu re of a resist , T Figure 1: 300mm wafer stage of the excimer abla- tion stepper tool ELP300.

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