Chip Scale Review - November December 2019

4 Chip Scale Review November • December • 2019 [] Stacking technologies: the road ahead By Favier Shoo [Yole Développement (Yole), part of Yole Group of Companies] h e eme r g i n g n e e d f o r a s m a r t h i g h - p e r f o r m i n g ecosystem requires disruptive capabilities such as artificial intelligence (AI), mass data transfer and lightning-fast connectivity, which largely depend on the underlying technologies. Consequently, there are new developments on the technology front, with the resurgence of existing through-silicon via (TSV) technologies, together with significant innovation in both high-end TSV and TSV-less platforms. Undoubtedly, the industry is coming to accept a new path to enable these digital transformation- led technical requirements and that is through stacking technologies, instead of relying on node scaling. High-performance computing (HPC), AI computing, cr ypto mining, data center computing, big data analyses, and the like, all require computing capabilit ies with low latency, high speed, and low power consumption. Today’s packaging technologies, such a s TSV, ma ke t he s e r equ i r eme nt s achievable combined with foot print r e d u c t i o n o n a c c ou n t of ve r t i c a l stacking. TSV technology is widely used in memory and in Si interposers. When we combine these two functionalities, we have hardware that can meet HPC requirements. TSVs in both memory and interposers are widely used with g r aph ics proce ssi ng un it s (GPUs). This was one of the f irst hardware appl icat ions for bot h t ech nolog ie s (interposer and high-bandwidth memory [HBM]). TSVs became more and more desirable with the entrance of HBM to the market considering the performance it can achieve with a reduced footprint. Presently, TSV technology is widely used in HPC applications — in what we call the high-end market — where cost is initially less critical on account of its stringent requirements. Hybrid bonding and 3D system-on-chip (SoC) will also have an impact on this market in the coming years, as players like Xperi, together with their partners, are working on implementing hybrid bonding in HPC hardware. Nevertheless, there is still much that needs to be demonstrated in terms of what TSV technology can do, for example: 1) Can it be used for very fine-pitch applications (<10µm)?; 2) Can it demonstrate higher reliability, which would enable its use in markets other than the HPC and high-end segments (e.g., in the automotive market)? Furthermore, can the cost/price of using TSV technology can be reduced further so that increased adoption in different mid-/low- end applications can be achieved. Although TSV technology is already established in mid-/low-end applications (e.g., CMOS image sensors [CIS]), its applications have to become more widespread in computing for consumer and enterprise applications in order for additional cost/ price reduction to take place. T h e r e a r e a l t e r n a t i ve s t o TSV interposers, and these depend on the final application, the field of use, parameters, dimensions and requirements. Some technologies are more expensive than others and are therefore more suitable for the high-end market than for mid-/ low-end markets. Most of the outsourced s em i c ondu c t o r a s s embl y a nd t e s t suppl ie r s (OSATS) a re developi ng proprietary solutions. If we dig into the details of each of those technologies, there are many similarities between them. Some are differentiated by the time in the process flow, others by changing the process step order, others still by the chip orientation. But the global technologies are quite similar and can, for the most part, be categorized as a sort of fan-out (FO) technology (e.g., Silicon Wafer Integrated Fan-out Technology, or SWIFT ® , fan-out chip-on-substrate [FoCoS], integrated fan-out [InFO] with substrate, and silicon-less interconnect technology [SLIT]). The cost, together with the performance and footprint of each and every one of these technologies, are three of the key parameters that the customers will be looking at when choosing between those solutions. Other technologies, like hybrid bonding and 3D SoC, can be alternative or additional technologies for the memory devices intended for the HPC market. At the moment, both technologies are still in R&D for these types of applications (hybrid bonding is already used in CIS). We believe that 3D SoC will begin small- volume production in 2019, with TSMC as the first player to propose this technology (die-to-wafer). Market growth forecast The markets delivering exceptional g r ow t h t h e s e d a y s t e n d t o b e i n a d v a n c e d p a c k a g i n g w i t h i n t h e semiconductor sector, and one of the fastest-growing platforms is stacking technology. The stacking technology ma r ke t i s p r o j e c t e d t o r eg i s t e r a compound annual growth rate (CAGR) of 26% from 2018 to 2024, to be valued at $6.2 billion in 2024 [1]. Stacking technology in automotive will be the fastest-growing market for the next f ive years, with its market size expanding at a compound annual growth rate (CAGR) of 125% between 2018 and 2024. This is because higher computing performance will be required (edge computing), while still subject to stringent automotive regulations in terms of reliability. Adoption is expected in CIS, light emitting diode (LED), and devices in power applications for electric vehicle/hybrid electric vehicle (EV/ HEV) needs, in the form of embedded die-in-substrate. Stacking technology in the HPC and networking markets is showing strong development—secu r i ng t he second highest g rowth at 34% CAGR f rom $446M in 2018, to $2,619M in 2024 [1]. This market comprises technologies such as 3D stacked memory (HBM and 3DS), 2.5D inter poser, and 3D SoC. These technologies also provide a huge oppor t unit y for telecoms/consumer market players to increase their presence in the enterprise market and to thereby sustain their long-term growth. T