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Chip Scale Review September • October • 2017


Photonic modules for data centers require

cutting-edge technologies

By Stéphane Bernabé, Olivier Castany, Bertrand Szelag, Benoît Charbonnier

[CEA-Leti within IRT-Nanoelec]

, and

Marc Epitaux

[SAMTEC Inc., within IRT-Nanoelec]

he cont i nuous i nc rea se of

worldwide internet traffic has

led to the development of mega

data centers to manage the huge amount

of information to be stored, processed, and

routed. This has resulted in the mass adoption

of optoelectronic devices at every level of

the global network. This is particularly true

in the aforementioned data centers, in which

parallel optics vertical cavity surface emitting

laser (VCSEL)-based transceivers operating

at 25Gbps per channel are now commonly

used to connect switches racks at distances of

several hundreds of meters.

The next-generation of data centers,

exhibiting dimensions equivalent to that of

several soccer fields, will have to manage

ever increasing aggregated data rates over

distances measured in kilometers. This

requires new optical components to be

developed with long-range single-mode

optical fiber transmission, and likely the

adoption of wavelength division multiplexing

(WDM) techniques to increase the overall

bandwidth carried on a single fiber. These

last two characteristics are not manageable

by VCSEL modules even though they have

the capability to be directly modulated at data

rates as high as 25Gbps and carry advanced

modulation like PAM4. Indeed, 850nm

wavelength VCSEL modules are limited to

multimode fiber links that are challenged by

modal dispersion in long ranges and byWDM

filtering packaging implementation.

As a result of the situation described above,

two integrated photonics technologies are

now competing to share the market of next-

generation hyper-scale data centers, as well

as data center clusters that are separated by

several dozen kilometers: InP-based circuit

devices, and silicon photonics devices

(using silicon-on-insulator [SOI]) wafers as

substrates). The latter emerged at the turn

of the century and the multiplication of

industrial players in the last five years (Intel,

Cisco, Mellanox, and others) making it a

more mainstream technology. This trend

will be accelerated in the coming years by

the requirement for integrated photonics to

provide terabit per second optical transmission

to electrical switches, which are expected to

offer ever increasing bandwidth: 400Gbps for

the next Ethernet interconnect link standards,

to 25.6Tbps data rate in the next 10 years.

Challenges for Si photonics

To address these challenges, silicon

photonics integrated circuits (Si-PICs)

possess several advantages. First, using a

sub-micrometric silicon waveguide allows

integrating miniature optical structures,

like light modulators, WDM filters, and

photodiodes when additional epitaxial

germanium is used. This makes silicon

photonics capable of providing densely

integrated complex circuits, like multi-channel

transceivers, high radix optical switches,

and so on, on a few square millimeters

of a chip. As an example, a 16-channel

integrated multiplexer (whose typical size is

around 3cm using glass technologies) has a

maximum dimension of 1mm when using

integrated Si-PICs that use sub-micron, high

refractive index contrast waveguides. On

top of that, silicon photonics leverages the

CMOS industry foundry fabrication lines,

as the aforementioned optical functions can

be processed on a 300mm wafer using deep

ultraviolet (DUV) lithography. As a result,

silicon photonics is particularly well suited for

mass production with high yields leading to a

substantial economy of scale.

Beside the chip fabrication itself, a

reduction of the cost related to the circuit

testing is also obtained by wafer-level testing

capabilities of the silicon photonics circuits.

For example, CEA Leti performed the

functional testing of circuits as complex as

QPSK (a high-level transmission standard

used in long-haul fiber telecommunication

network) transmitters using a reconfigurable

probe test station from Cascade with

embedded test equipment fromKeysight.

Because silicon photonics is an emerging

technology, several industrialization

challenges remain to be addressed. The first

one is design automation. Photonics circuits

do not follow the same design rules as

those from the CMOS industry. As a result,

electronic design automation (EDA) tools need

to be updated to integrate the specific design

rules, providing photonics-friendly design

rule check (DRC) procedures. In addition,

SPICE-like models of the devices need to be

developed for photonic building blocks to aid

circuit designers working to optimize their

circuits for a given technology platform (i.e.,

process design kits, or PDKs). IRT Nanoelec

is a French government-funded consortium

gathering industrial companies (ST, Mentor

Graphics, SAMTEC), a R&D research

lab (CEA Leti), and academics (CNRS) to

build the necessary libraries to support this

activity. IRT Nanoelec has invested a great

deal in this activity, and these libraries will

be made available in Mentor Graphics’ Pyxis

environment, as well as to customers through

multi-wafer projects offered at CMP (a French

wafer broker company).

The second challenge is the laser

integration: for this topic, IRT Nanoelec

is developing a technique whereby III-V

material is bonded over the SOI wafer, and

then post-processed with CMOS-compatible

technology in order to define heterogeneous

single-mode lasers.

Finally, the last goal of IRT Nanoelec is to

develop a novel packaging platform for silicon

photonics optical engines that can be placed

closely to a host chip and facilitate optical fiber

connection. Typical links of 200 or 400Gbps

are targeted to provide a total bandwidth

of 6.4Tbps for a host chip like an Ethernet

switch or a field-programmable gate array

(FPGA) device. Challenges to overcome will

be long manufacturing cycle time, high bill

of material (BOM) costs (which will decrease

as the technology is adopted), and scalable

methods of packaging photonic modules.

This new generation of optical module,

sometimes referred to as “mid-board optical

modules” (MBOM), requires several

advanced packaging techniques to be used

for the Si-PIC integration. This is directly due

to the electronic/photonic integration, fiber

optic coupling, and high number of I/Os to be