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37

Chip Scale Review September • October • 2017

[ChipScaleReview.com]

Lithography challenges for panel-level packaging

By Jack Mach

[Rudolph Technologies]

, and Ognian Dimov

[FujiFilm Electronic Materials, USA]

he semiconductor indust r y

d e v e l o p e d a r o u n d a

technology based on creating

d e v i c e s on r ou nd s i l i c on wa f e r s .

I n re cent yea r s , dev ice pa ckag i ng

technologies for these devices have

become an important consideration in

allowing the industry to continue to

satisfy consumer demand for increasing

performance in ever shrinking space.

By default, many of these packaging

technologies were developed for round,

silicon wafer-like substrates, however

there are significant advantages to be

derived from using larger, rectangular

substrates, commonly refer red to as

panels. Panel-level packaging (PLP)

brings its own set of challenges, and

its optimization requires the use of

equipment and materials specifically

designed to meet them.

Efficiency and throughput benefits

Square die do not fit well on round

s u b s t r a t e s . T h e r e i s a n i n h e r e n t

ineff iciency near the wafer’s edge,

wh e r e s q u e e z i ng a s ma ny d i e a s

possible onto t he wafe r i nev it ably

results in par t of the exposure f ield

f a l l i ng u s ele s sly i n t he exclu sion

zone, or off the wafer entirely. On a

rectangular substrate, the rectangular

pattern from the mask can fit perfectly,

u lt ima t ely i nc r e a si ng t he ave r age

numb e r of d i e p e r ex p o s u r e a nd ,

by extension, the throughput of the

exposure process.

Unlike silicon wafers, panels can be

produced easily at almost any size. A

larger substrate increases throughput

by reducing the nonproductive time

spent exchanging substrates. Moreover,

t he same con side r at ion s t hat have

h i s t o r i c a l l y d r i v e n i n c r e a s e s i n

wafer size also apply to non-round,

non -wa fe r s ub s t r a t e s , po t e n t i a l l y

p r ov i d i ng s ub s t a n t i a l g a i n s f r om

u si ng la rge pa nel s t h roughout t he

manufacturing process.

A mo d e l d e s i g n e d t o c omp a r e

300mm round substrates with 650mm

X 550mm panels [1] demonst r at ed

sign if icant benef its. The improved

fit between die and substrate resulted

i n r o u g h l y 10% i mp r ov eme n t i n

su r face utilization. The larger size

of the substrate and the improved fit

between the mask and substrate reduce

the transfer overhead by 5X. In this

comparison, the panel-based process

was estimated to reduce lithography

c o s t p e r d i e by a s mu ch a s 4 0%.

Anot he r s t udy [2] e s t imat ed even

greater cost reductions with fur ther

increases in panel size.

Challenges/solutions

Suppliers and device manufacturers,

wo r k i n g t o d e v e l o p p a n e l - b a s e d

p a c k a g i n g p r o c e s s e s t h a t t a k e

advantage of panels’ inherent benefits,

face a var iet y of challenges, which

can be grouped conveniently into two

categories: equipment and materials.

Equipment.

Advanced packaging

(AP) lithography conf ronts a set of

ch a l le nge s t h a t a r e u n ique t o t he

a p p l i c a t i o n . Fe a t u r e s i z e s r a n g e

f r o m m i c r o m e t e r s t o h u n d r e d s

of mic r ome t e r s a nd of t e n r e qu i r e

photoresist or dielectric layers much

thicker than those found in front-end

photol it hog r aphy. The l it hog r aphy

system must be able to supply enough

energy to activate the photosensitive

ma t e r i a l (e . g . , r e s i s t , p o l y i m i d e ,

dielect r ic, etc.), while mai nt ai ni ng

focus throughout the thicker layers to

precisely control critical dimensions

(CD) a nd sidewa l l p r of i le s . Some

types of photosensitive materials emit

sig n if icant amount s of ga s du r i ng

exposure that can contaminate optical

elements located close to the wafer

surface. A wide variety of substrates

a r e u s e d , i ncl ud i ng r e c on s t it u t e d

wafers (i n which separated die are

embedded in a polymer compound),

glass, and more. The substrates may

exhibit several millimeters of war p,

signif icant die-to-die displacement,

a nd s u b s t a n t i a l i n t e r- a nd i n t r a -

d ie t opog r aphy re su lt i ng f rom t he

embedding and bumping processes.

T he ex p o s u r e t o ol u s e d i n t h i s

s t u d y ( J e t S t e p

®

S35 0 0 , Ru d o l p h

Technologies) is specifically designed

t o add re ss t he se chal lenge s [3]. It

has a large exposure f ield (52mm X

66mm) and provides a combination of

resolution and depth of focus optimized

f o r t h e f e a t u r e s i z e s a n d r e s i s t

thicknesses used in AP applications.

A large working distance (between

the objective and the substrate) greatly

reduces the risk of contamination and

the need for maintenance, and allows

r oom fo r a n on - t he -f l y au t ofo cu s

sys t em. The 2X opt ica l r educ t ion

reduces the cost of masks. The optical

design permits fast, easy adjustments

of focus, alignment and magnification

to accommodate war page and other

var iations in subst rate topog raphy.

The stage and substrate handler are

specifically designed to transfer and

f latten large panels.

The system is also designed to work

within a feed-forward metrology loop

that measures positioning errors of die

on the substrate outside of the exposure

tool. Th is approach elimi nates t he

need to real ign t he exposu re f ield

within the stepper, which otherwise

may account for as much as two thirds

of an exposure cycle [4].

Mater ia l s .

The wa r page t y pical

for large panels also presents several

se r ious chal lenges for l it hog r aphy

processes from a materials perspective.

Fo r a d v a n c e d a p p l i c a t i o n s , t h e

requ i rement s for h igher resolut ion

have driven film thicknesses down to

~5.0µm, with resolution requirements

c u r r e n t l y a t 5 . 0 µm , a n d 2 . 0 µm

performance expected to be required

in the very near future. Suppressing

t he s t r e s s a nd wa r p a ge of p a nel s

requires dielectric materials with low

cu r i ng temper at u res (<200°C) and

low curing shrinkage. Processing of

such thin films on large format panels

with different surface roughness and

T