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Chip Scale Review September • October • 2018


Creating planar embedded RDL structures without CMP

By Richard Hollman


; Habib Hichri, Markus Arendt

[Suss Microtec Photonic Systems]


Ognian Dimov, Sanjay Malik

[Fujifilm Electronic Materials]

a c k a g i n g t e c h n o l o g y i s

increasingly migrating to fan-

out architectures, in many cases

with multiple chips in a package. Current

and projected designs require multiple

redistribution layers, in some cases

between 5 and 10 layers, with conductor

linewidths down to 2µm and via openings

below 10µm (

Figure 1


The high-density packaging


Traditional organic flip-chip substrates

are encountering challenges to scale to

these dimensions. Photosensitive spin-on

dielectrics for via formation, together with

redistribution layer (RDL) patterned with

photoresist, face serious technical challenges,

causing reliability and pattern integrity

concerns (

Figure 2

). Free-standing RDL

lines with <= 2/2µm L/S size may cause

electromigration concerns, and removing

the seed layer from the narrow trenches is

almost impossible, or causes severe undercut

to the RDL lines. The non-planar surface

presents an additional challenge for the next

redistribution layer because it requires a

larger depth of focus for the exposure system,

which in turns limits its resolution capability.

Finally, warpage of the substrate during

processing is increasing with additional RDL

layers, so careful selection of the material

with respect to thermal properties is key.

Dual-damascene process

A viable solution to overcome these

challenges is to apply a dual-damascene

f a b r i c a t i on p r o c e s s t o d e l i ve r a n

embedded RDL structure. This process

is well known from CMOS fabrication in

the front end. A polyimide is patterned

to create RDL trenches, but not stripped

after development (

Figure 3

). A seed

layer is deposited on the patterned and

fully cured polyimide, followed by Cu

electroplating to fill the trenches and

vias. Because the seed layer is present

everywhere on the polyimide surface,

plating also occurs on the top surface as

well as the trenches and vias. Once

the desired features are filled, it

is necessary to remove the excess

Cu and seed layer, which is done

using the chemical-mechanical

planar ization (CMP) process.

This CMP step adds complexity

and cost to the process flow, and

is a serious impediment for the

adoption in advanced packaging.

To overcome these barriers, this

article features a cost-saving dual-

damascene fabrication process to

create embedded redistribution

layers for fan-out packaging. This

process uses mask-based excimer

laser ablation to pattern trenches and

vias, a non-photosensitive dielectric with

excellent thermal and resolution properties,

and an innovative plating process that

achieves planarization without the need

for CMP. We report experimental results

where RDL trenches were filled with less

than 0.5µm overburden, which is easily

removed by a combination of de-plating

and either wet etching or excimer laser

ablation, with no damage to the embedded


Excimer laser ablation patterning

One of the key enablers for the improved

embedded conductor process is patterning

of the dielectric layer by excimer laser

ablation tool (

Figure 4

). As reported in [1],

this provides several important advantages

over the photosensitive polyimide process:

- The d ielect r ic mat e r ial can be

s e l e c t e d f o r i t s m e c h a n i c a l

properties, and thermal and chemical

stability. The potential to use non-

photosensitive material gives access

to a wider material selection and can

help to significantly reduce material

cost. The abilit y to use a wider

variety of dielectric material will

also provide relief with respect to

wafer warpage.

- The dielectric material is patterned

after final curing rather than before,

minimizing dimensional and profile

changes and allowing smaller features.

- The development step and the descum

process are eliminated along with

associated equipment and materials.

- Vias and trenches can both be formed

in one process step, requiring only

a reticle change while the wafer is

chucked on the tool.

- The technology can also be used to

remove thin residual metal layers

on t op of a poly imide su r face.

Th is process step is c r it ical to


Figure 1:

Multiple interconnect layers in

µ-out packaging.

Figure 2:

Conductors patterned with photoresist,

which is stripped after patterning.

Figure 3:

Conductors embedded in polyimide.

Figure 4:

Excimer laser ablation stepper tool (Suss Microtec

Photonic Systems).