Chip Scale Review September • October • 2018[ChipScaleReview.com]
the successful creating of planar
embedded RDL structures without
CMP, as described later in this article.
Excimer laser ablation patter ning
provides a unique flexibility not available
i n o t he r pa t t e r n i ng me t hod s , a nd
this f lexibility turns out to be critical
i n mak i ng th is process successf ul.
This ablation process is available and
validated for a variety of substrates,
Dielectric for embedded conductor
As ment ioned above, t he u s e of
ablation patterning permits a choice
of dielectric that is not restricted to
phot os en sit ive mat e r ia l s. For t h i s
work, we used FCPi-2100 polyimide
from Fujifilm Electronic Materials. It
exhibits excellent physical, thermal,
electrical and chemical properties for
this application, as shown in
The thermal stability is illustrated in
, showing negligible change in
patterned feature size with baking. The
thermal expansion coefficient can be
modified to match a variety of substrates,
including panels. It has also been shown
to be compatible with a wide variety of
solvents, acids and bases, including those
that are likely to be encountered in the
Metallization involves two separate
processes: vacuum deposition of a seed
layer, and electroplating to fill the vias
Seed layer deposition.
The seed layer
provides a current path to a contact at
the edge of the wafer or panel during the
plating process. However, it serves the
equally critical function of providing
a d he s ion b e t we e n t he u nde r l y i ng
polyimide surface and the conductors,
which will be plated. Without good
adhesion, delamination of the conducting
lines and vias may occur after plating or
during downstream process steps.
For this process, the seed layer was
deposited using a TEL NEXX Apollo
PVD tool. Adhesion was guaranteed
by the use of an Ar-based inductively
coupled pl a sma ( ICP) e t ch befo r e
deposition to clean and activate the
polyimide surface, and by depositing the
Ti and Cu in the same chamber with no
break in vacuum.
In previous versions
of the embedded conductor process,
CMP is required to remove excess metal
deposited in the electroplating step.
So, to eliminate CMP it is necessary to
minimize the excess metal to the point
where it is possible to remove it by
Us i n g a mo d i f i e d ve r s i o n o f a
commercial TSV plating chemistr y,
an efficient bottom-up plating process
was developed (
process can fill trenches 6µm deep with
overburden less than 0.5µm.
We can beg i n t o u nde r st and t he
mechanism for bottom-up filling in this
case in terms of TSV plating, although
there are important differences, as we
shall see. A TSV plating chemist r y
i ncl ud e s t h r e e o r g a n i c a dd i t i ve s:
an accelerator, which catalyzes the
deposition reaction; a leveler, which
strongly inhibits this reaction; and a
suppressor, which moderates the surface
kinetics of the two other species. In TSV
plating, bottom-up filling is achieved
because the leveler, which is a slower-
diffusing molecule, is initially present
in a much smaller concentration at the
bottom of the via than at the top surface.
So, the plating deep within the via is
dominated by the accelerator, while
plating is suppressed on the top surface
and the upper parts of the sidewall.
For embedded conductor structures,
the diffusion distances are a few microns
at most, and aspect ratios are 1:1 or less.
So, segregation of the leveler purely
due to diffusion does not appear likely.
However, the increase in effective surface
area presented to the solution, from the
sidewalls of the ablated features and the
Thermal stability of FCPi-2100 (Fujifilm
Properties of FCPi-2100 polyimide (Fujifilm
2–3μm trenches filled using a bottom-up
Surface evolution during plating showing
bottom-up trench fill.
Illustration of the “leveler depletion”
hypothesis to explain bottom-up plating:
a) initial state, b) at start of plating, c) leveler and
accelerator concentrations adjust, and d) steady-state
plating condition. The suppressor is not shown here.