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Chip Scale Review September • October • 2018


roughness of the ablated surfaces, may

cause a modest increase in the initial

consumption of leveler in these locations,

plus a modest geometric buildup of

accelerator as the Cu surface evolves.

Once established, this can become a

self-perpetuating process (

Figure 8


with leveler-dominated plating at the

top surface and accelerator-dominated

plating in the ablated features.

This plating process exhibits the

phenomenon of “momentum plating,”

i.e., the deposition proceeds at a faster

rate on the trench feature even after

the trench has been completely filled.

This phenomenon is also seen when the

plating includes a via to connect two

layers (

Figure 9


Challenges for a planar process

There are two cr itical challenges

which must be met in order to provide

a practical process. First, while the

overbu rden is ver y small, it is not

zero, and this metal, plus the original

seed layer, must be removed before

s ub s eque nt p r oc e s si ng c a n oc cu r.

Second, the efficient bottom-up plating

is ver y sensit ive to t he si ze of t he

ablated features. In our tests, trenches

up to 10μm in width could be f illed

with a reasonably small overburden,

but for 15μm and wider lines the fill

was incomplete.

Residual metal removal.

The first

challenge, removal of residual metal

without CMP, has been demonstrated

in two different ways. In both cases,

the metal removal begins in the plating

step itself. Once the ablated features

are filled, the plating current can be

reversed. Nearly all of the Cu can be

removed from the top surface without

compromising the plated conductors

themselves. This leaves a very small

residue of Cu to be removed, along

with the Ti adhesion layer. The second

step, to complete the residual metal

r emov a l , h a s b e e n d emo n s t r a t e d

w i t h t wo d i f f e r e n t a p p r o a c h e s


Figure 10

): either with a brief wet etch,

or by excimer laser ablation. Although

metal layers of 1μm or greater thickness

ser ve as an ef fect ive etch stop for

excimer laser ablation, very thin layers

on a polyimide surface can be efficiently

removed. Either approach provides

the desired savings in equipment and

materials cost and process complexity

from elimination of CMP.

Feature size dependence.

In larger

features, an efficient bottom-up plating

becomes more challenging because

the concentration of the leveler at the

bottom of the feature is significantly

higher than in smaller features, which

leads to a slower plat i ng speed. A

pot ent ia l solut ion t o t h is p roblem

is to modif y the su r face text u re of

these larger features that allows the

accelerator to dominate the plating

process inside the patterned structures.

We are currently investigating suitable

methods for surface texturing that will

allow preferential bottom-up plating in

large features, as well as small lines and

vias. The plated features should ideally

be nearly f lush with the surrounding

surface, so that, after application of the

next layer of dielectric, a sufficiently

planar surface is presented for the next

sequence of RDL layer formation.


Planarization is an essential part of

any multilayer RDL stack structure.

Embedded conductors are a means to

this end, but deposition processes to this

point have included significant metal

on the top su r face, requi r i ng CMP

for removal. This not only represents

an added expense in equipment and

materials, but may be a barrier to panel

applications. We have shown that, with

the r ight combination of mater ials,

patterning method, and metallization,

an embedded conductor structure can

be fabricated with minimal residual

met al, wh ich can be removed wit h

simpler and less expensive techniques.

One key aspect of this is the use of

bottom-up electroplating, adapted from

TSV processing.


1. H. Hichri, M. Arendt, “Excimer laser

ablation for microvia and fine RDL

routings for advanced packaging,”

Chip Scale Review,

Oct. 2017.

2. R. Hollman, O. Dimov, S. Malik, H.

Hichri, M. Arendt, “Ultra fine RDL

structure fabrication using alternative

patterning and bottom-up plating

processes,” ECTC Proc. June 2018.

3. R. Akolkar, U. Landau, “Mechanistic

Analysis of the ‘bottom-up’ fill in

copper interconnect metallization,”

J. Electrochem. Soc. vol. 156 no. 9


4. P. Vereecken et al., “The chemistry

of additives in damascene copper

plating,” IBM J. Res. & Dev. vol. 49

no. 1 (2005).


Richard Hollman received his PhD in

Physics from Stanford U. and is Principal

Process Engineer at TEL NEXX Inc.; email

Habib Hichri received his PhD in

Chemical Engineering f rom Claude

Be r n a r d U., Lyon , Fr a nc e , a nd i s

Applications Engineering Director at Suss

Microtec Photonic Systems Inc.

Markus Arendt received his PhD in

Economical Engineering from U. of

Heidelberg, Germany, and is President at

Suss Microtec Photonic Systems Inc.

Ognian Dimov received his MS in

Physics from Sophia U., Bulgaria, and

is Senior Associate

Engineer at Fujifilm

Electronic Materials.

S a n j a y M a l i k

received his PhD in

Mat e r ia l s Science

a n d E n g i n e e r i n g

from Indian Institute

o f T e c h n o l o g y ,

Kha r ag pu r, I nd ia ,

a n d i s D i r e c t o r

o f New Bu s i n e s s

D e v e l o p m e n t a t

Fujif ilm Electronic


Figure 9:

Cross section SEM of a bottom-up plated

dual-damascene structure.

Figure 10:

Residual metal removal without CMP: deplating plus wet etch or ablation.