Chip Scale Review September • October • 2018[ChipScaleReview.com]
with respect to any final inspection process. Keeping this process
in place without the need for mechanical dicing screening just adds
unnecessary cost to the final product.
Step 3 is to strategically implement a final inspection
capable die attach or tape and reel process to successfully screen parts
for issues encountered during die pick processing. In general, die are
processed without issue during the full front-end-of-the-line (FEOL)
flow only to be damaged during the die pick process. Once this process
is complete, detection capabilities today are limited. Implementing
visual inspection at this point in the process with a control system to
flag lots that have pick issues or trigger limits puts a system in place to
control and prevent the customer from receiving damaged parts.
A drastic change is needed in the semiconductor back end assembly
flow. With today’s push toward higher resolution images, today’s
processes are creating cases where overkill and dispositions are
becoming a way of life for the back-end-of-line (BEOL) assembly areas.
This trend cannot continue long term, as fundamental changes
with the dicing processes and technologies used continue to
improve. This article discussed the use of new dicing technologies
and proposed the elimination of long-standing expensive
inspections that still typically do not prevent or contain damage
created at the pick processes downstream. The key to solving the
challenges is to fix these chipping issues, and direct process controls
and containment procedures at the die attach and tape and reel level
to detect out of control set-ups and pick issues during processing.
Our collective goal is to eliminate chipping at the source and
redirect the focus of long-standing inspections to stop and contain
downstream processes. If we do that, we can resolve the many
“dppm” issues our industry experiences today, which are where
the majority of the challenges arise when customers raise the flag.
1. M. Todd Wyant, “Wafer chip-scale package cost reductions,”
Chip Scale Review
, Vol. 19 No. 2, pp. 54-56.
Todd Wyant earned a BSME from Purdue U. in Mechanical
Engineering and a Six Sigma Black Green Belt from AIT; he is the
Manufacturing Technology Manager at Texas Instruments; firstname.lastname@example.org
a) Fault tree for chipping factors; b) Common edge chip; c) Corner