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Chip Scale Review September • October • 2019

[ChipScaleReview.com]

Integrating ultra-thin Si dies within a flexible label

By Jean-Charles Souriau

[CEA-Leti]

ecent developments in the

i nteg rat ion of ult ra-t h i n

silicon dies within a flexible

film lead to a new paradigm. Indeed,

thanks to the thinness and flexibility of

devices, it is conceivable that functions

can be added around any object without

changing its aspect [1-5]. Currently, only

electronic tracks between components are

flexible in the major flexible electronic

products on the market. This is due to the

fact that the silicon components are already

packaged or are too thick. In order to get

fully-flexible devices, silicon dies have

to be thinned to less than 100µm. Three

formats can be processed to build flexible

electronic systems: ribbon, panel or wafer.

The first two formats are well-adapted for

large devices, are low cost, and allow high

throughput. Patterning resolution in these

formats is only fair, however. Working with

silicon wafers helps achieve high resolution

of integration. Silicon wafers are well-

suited for flexible fan-out packaging, which

helps build a heterogeneous, flexible system

that combines a panel substrate, including a

printed device and interconnection network

with a silicon electronic die integrated

within a small flexible label.

New process development

One challenge is to offer a process

compat ible wit h ba r e d ie s. A new

technology called ChipInFlex proposes

the integration of ult ra-thin silicon

dies within a f lexible label made on

a wafer carrier in the manufacturing

microelectronic line [6]. It was chosen for

the electrical interconnection gold stud

bumps because it enables the hybridization

by thermocompression at low temperature

(<150°C) and it is compatible with the

polymer (

Figure 1

). Indeed, the use of

solder bump, such as SnAgCu, was not

conceivable. Moreover, stud bumps also

can be made on bare dies. The choice of

the flexible material in which to integrate

silicon dies is critical. In the ChipInFlex

study, we tested the commercialized

photosensitive siloxane polymer SiNR,

which is available in spin-on or dry

film, and has low stress and a low-cure

temperature. The manufacturing process

experiment is detailed in

Figure 2

.

The carrier is a 200mm silicon wafer,

which was treated to get a temporary

adhesion layer. A SINR film 30µm or

80µm thick was deposited by spin coating

or laminating. The electrical network

was made of WN

50nm

/Au

200nm

metallic.

A 50µm-thick coating of silver glue was

deposited on pads by serigraphy. Dies

were aligned and attached on the wafer

using a DATACON f lip-chip tool. The

equipment system enables dispensing dots

of polymer glue and then aligns and mounts

the components under a combination of

heat and pressure. In this study, the Epo-

Tek E505 glue was used because of its

useful viscosity properties as a function

of temperature. Stud bumps can easily go

through the glue and contact gold pads on

the substrate. The bonding was performed

in two steps. All dies were attached with

the flip-chip tool and then collectively

bonded using an EVG thermocompression

bonder. Collective thinning, including

coarse and fine grinding, was performed

R

Figure 1:

Flip chip Interconnection using gold

stud bump.

Figure 2:

Wafer-level process flow of silicon dies’ encapsulation.

Figure 3:

Gold stud bumps on a test vehicle.